How to reduce "Core static thermal dissipation" from fpga de

[Pedro Lazaro]

Hello sirs,

I'm working on this problem for some days, and I'll be grateful if anyone could help.

I have a fpga cyclone II design and I need analyze its power consumption.

My problem is:
In these results of power analysis by the powerplay analyzer
************************************************************
Total Thermal Power Dissipation --------288.49 mW
Core Dynamic Thermal Power Dissipation 23.05 mW
Core Static Thermal Power Dissipation 219.88 mW <------ here!
I/O Thermal Power Dissipation --------45.56 mW
Power Estimation Confidence High: user provided sufficient toggle rate data
*************************************************************
the Core static thermal power dissipation is very high comparing with the other rates. And, by what I know, that occur because the fpga components which I'm not using at the design are consuming power.

So, I need to know if there is any way to reduce this dissipation. Maybe disabling these components or elaborating better my design.

I'm searching pll stuff and clock managements workarounds, but I'm not sure if this is the correct way to solve my problem.

Thanks by your attention.

Pedro Lázaro.


My environment.
Softwares I'm using in my problem:
For synthesis: Quartus II 9.1
For the power analysis: PowerPlay Power Analyzer tool in Quartus
For simulation at gate level: Modelsim-altera 10.0c
SO: Ubuntu 12.04

 

On Monday, May 19, 2014 8:29:25 AM UTC+3, Pedro Lazaro wrote:

Hello sirs,

I'm working on this problem for some days, and I'll be grateful if anyone could help.

I have a fpga cyclone II design and I need analyze its power consumption.

My problem is:
In these results of power analysis by the powerplay analyzer

************************************************************

Total Thermal Power Dissipation --------288.49 mW

Core Dynamic Thermal Power Dissipation 23.05 mW

Core Static Thermal Power Dissipation 219.88 mW <------ here!

I/O Thermal Power Dissipation --------45.56 mW

Power Estimation Confidence High: user provided sufficient toggle rate data

*************************************************************

the Core static thermal power dissipation is very high comparing with the other rates. And, by what I know, that occur because the fpga components which I'm not using at the design are consuming power.



So, I need to know if there is any way to reduce this dissipation. Maybe disabling these components or elaborating better my design.



I'm searching pll stuff and clock managements workarounds, but I'm not sure if this is the correct way to solve my problem.



Thanks by your attention.



Pedro Lázaro.





My environment.

Softwares I'm using in my problem:

For synthesis: Quartus II 9.1

For the power analysis: PowerPlay Power Analyzer tool in Quartus

For simulation at gate level: Modelsim-altera 10.0c

SO: Ubuntu 12.04

It looks like you (or your predecessors, or your boss) had chosen wrong FPGA device.
Low dynamic power indicates that device does virtually nothing. So, it almost certainly was possible to fit your task into much smaller device, e.g. EP2C20 or even EP2C5 instead of big device (what is it, EP2C70 ?) that you are using now.
As to your question, after device was chosen, very little could be done. The best you can do is to keep it at the lowest possible temperature - static power consumption strongly depends on the temperature.
Also there is a hope that Altera power estimator is to pessimistic.

 

[mnentwig]

Is there any legal way to lower the supply voltage?

---------------------------------------
Posted through http://www.FPGARelated.com

 

[rickman]

On 5/19/2014 1:29 AM, Pedro Lazaro wrote:

Hello sirs,

I'm working on this problem for some days, and I'll be grateful if anyone could help.

I have a fpga cyclone II design and I need analyze its power consumption.

My problem is:
In these results of power analysis by the powerplay analyzer
************************************************************
Total Thermal Power Dissipation --------288.49 mW
Core Dynamic Thermal Power Dissipation 23.05 mW
Core Static Thermal Power Dissipation 219.88 mW <------ here!
I/O Thermal Power Dissipation --------45.56 mW
Power Estimation Confidence High: user provided sufficient toggle rate data
*************************************************************
the Core static thermal power dissipation is very high comparing with the other rates. And, by what I know, that occur because the fpga components which I'm not using at the design are consuming power.

So, I need to know if there is any way to reduce this dissipation. Maybe disabling these components or elaborating better my design.

I'm searching pll stuff and clock managements workarounds, but I'm not sure if this is the correct way to solve my problem.

Thanks by your attention.

Pedro Lázaro.


My environment.
Softwares I'm using in my problem:
For synthesis: Quartus II 9.1
For the power analysis: PowerPlay Power Analyzer tool in Quartus
For simulation at gate level: Modelsim-altera 10.0c
SO: Ubuntu 12.04

I assume by now you know that the static power of an FPGA is not a
function of your design, but rather of the chip. To lower the static
current you need to change chips. Lattice makes the iCE40 devices with
static current in the 100 uA range. These are not large parts, but hold
a fair amount of logic. They also have a non-volatile configuration
storage if needed. Lattice also makes other devices that are low on
power consumption although not as low as the iCE40. Check out the XO2
and the XP2 lines.

--

Rick

 

[Marko Zec]

rickman <gnuarm@gmail.com> wrote:

On 5/19/2014 1:29 AM, Pedro Lazaro wrote:
Hello sirs,

I'm working on this problem for some days, and I'll be grateful if anyone could help.

I have a fpga cyclone II design and I need analyze its power consumption.

My problem is:
In these results of power analysis by the powerplay analyzer
************************************************************
Total Thermal Power Dissipation --------288.49 mW
Core Dynamic Thermal Power Dissipation 23.05 mW
Core Static Thermal Power Dissipation 219.88 mW <------ here!
I/O Thermal Power Dissipation --------45.56 mW
Power Estimation Confidence High: user provided sufficient toggle rate data
*************************************************************
the Core static thermal power dissipation is very high comparing with the other rates. And, by what I know, that occur because the fpga components which I'm not using at the design are consuming power.

So, I need to know if there is any way to reduce this dissipation. Maybe disabling these components or elaborating better my design.

I'm searching pll stuff and clock managements workarounds, but I'm not sure if this is the correct way to solve my problem.

Thanks by your attention.

Pedro L?zaro.


My environment.
Softwares I'm using in my problem:
For synthesis: Quartus II 9.1
For the power analysis: PowerPlay Power Analyzer tool in Quartus
For simulation at gate level: Modelsim-altera 10.0c
SO: Ubuntu 12.04

I assume by now you know that the static power of an FPGA is not a
function of your design, but rather of the chip. To lower the static
current you need to change chips. Lattice makes the iCE40 devices with
static current in the 100 uA range. These are not large parts, but hold
a fair amount of logic. They also have a non-volatile configuration
storage if needed. Lattice also makes other devices that are low on
power consumption although not as low as the iCE40. Check out the XO2
and the XP2 lines.

Well, Lattice XP2 is a neat chip indeed, but it doesn't really fall
into the "low static power consumption" category.

Marko

 

[rickman]

On 5/22/2014 1:54 PM, Marko Zec wrote:

rickman <gnuarm@gmail.com> wrote:
On 5/19/2014 1:29 AM, Pedro Lazaro wrote:
Hello sirs,

I'm working on this problem for some days, and I'll be grateful if anyone could help.

I have a fpga cyclone II design and I need analyze its power consumption.

My problem is:
In these results of power analysis by the powerplay analyzer
************************************************************
Total Thermal Power Dissipation --------288.49 mW
Core Dynamic Thermal Power Dissipation 23.05 mW
Core Static Thermal Power Dissipation 219.88 mW <------ here!
I/O Thermal Power Dissipation --------45.56 mW
Power Estimation Confidence High: user provided sufficient toggle rate data
*************************************************************
the Core static thermal power dissipation is very high comparing with the other rates. And, by what I know, that occur because the fpga components which I'm not using at the design are consuming power.

So, I need to know if there is any way to reduce this dissipation. Maybe disabling these components or elaborating better my design.

I'm searching pll stuff and clock managements workarounds, but I'm not sure if this is the correct way to solve my problem.

Thanks by your attention.

Pedro L?zaro.


My environment.
Softwares I'm using in my problem:
For synthesis: Quartus II 9.1
For the power analysis: PowerPlay Power Analyzer tool in Quartus
For simulation at gate level: Modelsim-altera 10.0c
SO: Ubuntu 12.04

I assume by now you know that the static power of an FPGA is not a
function of your design, but rather of the chip. To lower the static
current you need to change chips. Lattice makes the iCE40 devices with
static current in the 100 uA range. These are not large parts, but hold
a fair amount of logic. They also have a non-volatile configuration
storage if needed. Lattice also makes other devices that are low on
power consumption although not as low as the iCE40. Check out the XO2
and the XP2 lines.

Well, Lattice XP2 is a neat chip indeed, but it doesn't really fall
into the "low static power consumption" category.

Yeah, sorry, I forgot. It is the XO2 they are pushing for that along
with the iCE40 line.

--

Rick