How to recognize slot layer except adding one mask layer?

[Tech11]

Hello,everyone

Since there's no slot mask layers in my technology file, it's complicated to
add and then modify the existing design, is there any other way to recognize
slot layer? If I select polygones holed by metal, which will include those
ringed metal and it's difficult to keep back these status. How to find one
good way to do so?

Have a good day!

Best Regards,

Joffre

 

[vdvalk@rogers.com]

Joffre"

What you want to do is move away from the input conductor layer concept
and move into the are of sythesized layout.

What you are talking about is to add a new "LPPS" layer to cadence.
This is trivial to recognize.
Since it is new, it is unique. But this means you need to add it's
existance to all of the tools that
deal with the conductor.

(i.e. you want the actual conductor to have holes generated by a "Slot"
layer placed on top)

This operation is trivial to accomplish technically, but has all sorts
of problems that are associated with it.

You first need to create the infrastructure to let you design on this
slot layer.
(i.e. create the layer, add drc/tapeout support for it )

The next problem is to figure out how to make connectivity work.
( i.e. what is your plan for "pin" layers and "labels" and "contact"
layers, et ... )

Once you understand and have handled all of these issues, then you need
to modify the conductor itself.
You then need to update the connection command(s) to use the new layer.

Also you need to think about how this new modifed conductor interacts
with the device and parasitic
extraction.

All of these steps are simple, but you do need to consider each one and
handle them all.

-- Gerry

 

[Tech11]

Dear Gerry,

Thanks for your reply!

I do know this way and how to add layers to technology files, I wanna find
if there's any other way to do it without adding layers since some layout
engineers are working with the just technology file, if I add new layer,
they'll have to modify their design. Now they add slot holed by metal, it's
difficult to divide them from normal ringed metal.

Have a good day!

B.R.

Joffre

<vdvalk@rogers.com>
??????:1145631782.032548.179480@i40g2000cwc.googlegroups.com...

Joffre"

What you want to do is move away from the input conductor layer concept
and move into the are of sythesized layout.

What you are talking about is to add a new "LPPS" layer to cadence.
This is trivial to recognize.
Since it is new, it is unique. But this means you need to add it's
existance to all of the tools that
deal with the conductor.

(i.e. you want the actual conductor to have holes generated by a "Slot"
layer placed on top)

This operation is trivial to accomplish technically, but has all sorts
of problems that are associated with it.

You first need to create the infrastructure to let you design on this
slot layer.
(i.e. create the layer, add drc/tapeout support for it )

The next problem is to figure out how to make connectivity work.
( i.e. what is your plan for "pin" layers and "labels" and "contact"
layers, et ... )

Once you understand and have handled all of these issues, then you need
to modify the conductor itself.
You then need to update the connection command(s) to use the new layer.

Also you need to think about how this new modifed conductor interacts
with the device and parasitic
extraction.

All of these steps are simple, but you do need to consider each one and
handle them all.

-- Gerry