How to put part of one array into another

[none]

I have 2 arrays declared in my code :

type Array6Deep96Bit is array (6 downto 1) of std_logic_vector (95
downto 0) ;
type Array16Deep96Bit is array (16 downto 1) of std_logic_vector (95
downto 0) ;


In an instantiation of a block of code, I'd like to port the first 6
array words into the block:

port map (
BackplaneSerialDataIn => DataFromPackToMux(6 downto 1),

where BackplaneSerialDataIn is of type Array6Deep96Bit and
DataFromPackToMux is of type Array16Deep96Bit.

I'm using Aldec Active-HDL and it gives me an error stating "Actual
parameter type in port map does not match the port formal type
"BackplaneSerialDataIn"

I've tried different permutations of the instantiation such as
explicitly referencing the array index, but I either get the previous
error message or on that says "No actual specified for local port
"BackplaneSerialDataIn"

Any ideas on how to write this without having to expand out the array to
it's individual elements?

Thanks

Ron

 

[Brian Drummond]

On Thu, 11 Sep 2008 13:47:32 -0500, none <none@none.com> wrote:

I have 2 arrays declared in my code :

type Array6Deep96Bit is array (6 downto 1) of std_logic_vector (95
downto 0) ;
type Array16Deep96Bit is array (16 downto 1) of std_logic_vector (95
downto 0) ;

I'm using Aldec Active-HDL and it gives me an error stating "Actual
parameter type in port map does not match the port formal type
"BackplaneSerialDataIn"

You have made them different types. It might be possible (but ugly) to
force conversions between them; but it's supposed to be difficult.

But what if they were subtypes of a common ancestor? It makes sense to
use subtypes if you want to allow assignments between them, and separate
types if you want to prevent it.

type Array_Of_96Bit is array <> of
std_logic_vector (95 downto 0);

This is an unconstrained array. You can create different subtypes of it,
which are somewhat compatible with each other.

subtype Array6Deep96Bit is Array_Of_96Bit(6 downto 1);
etc.

By analogy with different sizes of std_logic_vector (which are distinct
subtypes, whether you give them explicit names or not), these too can be
assigned, sliced, etc.

That is, you can say

subtype big_word is std_logic_vector (95 downto 0);
type Array_Of_Big_Words is array <> of big_word;
subtype SixBigWords is Array_Of_Big_Words(6 downto 1);
subtype SixteenBigWords is Array_Of_Big_Words(16 downto 1);

(put all these declarations in a package and use it in everything on the
backplane... then )

SIGNAL DataFromPackToMux : SixteenBigWords;

port map (
BackplaneSerialDataIn => DataFromPackToMux(6 downto 1),

Basically state what you actually want, and let the type system help,
instead of fighting it. Anyone reading the code will have a better idea
of what it does, too.

- Brian

 

[KJ]

On Sep 11, 2:47 pm, none <n...@none.com> wrote:

I have 2 arrays declared in my code :

type Array6Deep96Bit    is array (6 downto 1) of std_logic_vector (95
downto 0) ;
type Array16Deep96Bit   is array (16 downto 1) of std_logic_vector (95
downto 0) ;

In an instantiation of a block of code, I'd like to port the first 6
array words into the block:

port map (
        BackplaneSerialDataIn => DataFromPackToMux(6 downto 1),

where BackplaneSerialDataIn is of type Array6Deep96Bit and
DataFromPackToMux is of type Array16Deep96Bit.

I'm using Aldec Active-HDL and it gives me an error stating "Actual
parameter type in port map does not match the port formal type
"BackplaneSerialDataIn"

This is what is known as data type checking. The entity parameter
BackplaneSerialDataIn is type 'Array6Deep96Bit', but you're trying to
give it DataFromPackToMux(6 downto 1) which is a slice of an array of
type 'Array16Deep96Bit', those elements being of type
'std_logic_vector (95 downto 0)'. Since these are two different types
you're getting the error.

Instead you might want to try out the following approach:

type Array96Bit is array(natural range <&gt of std_logic_vector (95
downto 0);
subtype Array6Deep96Bit is array (6 downto 1) of Array96Bit;
subtype Array16Deep96Bit is array (16 downto 1) of Array96Bit;

Now the new types 'Array6Deep96Bit' and 'Array16Deep96Bit' are arrays
of the same type and any slice of them will also be of that same type
(i.e. type 'Array96Bit').

It's confusing when you get started creating your types because you
tend to think of it in terms of the definitions of the types that the
thing is made up of. In this case you were looking at your new types
as both being simply different sized collections of the same type of
thing (std_logic_vector(95 downto 0). But a strongly typed language
does not allow for such syntax. It looks at the type that is expected
and expects to find something of that same type being assigned.
Things of type 'xyz' cannot be assigned to something that is of type
'abc' even if the definitions of those two types is identical.

What you need to do is just not look so deeply (i.e. don't look at the
definition of the new types when trying to deduce what the type
mismatch is), just look at the actual types being passed around. By
first defining a generic array type as I did ( i.e. 'Array96Bit') that
can be used to define any range of subtypes from it, you're writing
the code in a manner that it is type correct...and as you can see,
it's not that difficult or different from your original code.

Kevin Jennings