How to pipeline Loop Logic?

[Davy]

Hi all,

It's intuitive to pipeline a feed-forward combinational logic. But how
to pipeline the Loop without changing the timing?

For example, when I insert a reg to feed-forward logic, shall I delete
a reg in feedback logic at the same time?

And if the datapath logic is a iteration one(Logic A -> Logic B ->
Logic A -> Logic B ...)? How to do pipeline?

Any suggestions will be appreciated!

Best regards,
Davy

 

[Berty]

Generally speaking pipeline will help you work in faster frequency
however it will effect the latency.

If for example you need the result after one clock than you can't
insert extra FF/FF's to pipeline and still do it in single clock
(assume there is only one clock in the system).

Have Fun.

 

[Vinilkant Tejaswi]

you can try both clock edges.