How to perform a timing simulation in Modelsim with QuartusI

[ALuPin]

Hi newsgroup people,

I want to perform a timing simulation of an SRAM controller with
Modelsim (version Altera 5.7e) .
The background: With address, data and write strobe all changing
simultaneously, I am not sure whether the right data will get written
to the right location in the SRAM.

Right now I am performing a functional simulation. Since I am running
with timing check off, data should never be corrupted.

Since the SRAM controller is a central module in my design I have to
know exactly whether it will run correctly or not so that other
modules adapted to the controller will not have to be modified
belatedly.

It is for that purpose of operating on a boundary condition that I
want to add timing to my simulation to get a better idea of what will
happen in hardware.
I am working with Altera QuartusII software (version 4.0 SP1).

For the purpose of a timing simulation under Modelsim I would like to
know how to make settings in QuartusII to get the correct output files
and how to include them in Modelsim.

I would appreciate if you had the time to have a closer look at
http://mitglied.lycos.de/vazquez78

Thank you very much for your help.

 

[Andy Peters]

ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0405100255.9edda8b@posting.google.com>...

Hi newsgroup people,

I want to perform a timing simulation of an SRAM controller with
Modelsim (version Altera 5.7e)

I am working with Altera QuartusII software (version 4.0 SP1).

For the purpose of a timing simulation under Modelsim I would like to
know how to make settings in QuartusII to get the correct output files
and how to include them in Modelsim.

I'm sure this is all documented somewhere, so it's clearly time to
RTFM.

Basically, the fitter spits out a Verilog or VHDL model of your
design. This model has the port interface, but the innards are
replaced with the particular FPGA's low-level features and the proper
interconnects. By default, Quartus puts this file in the
<design_root>\simulation\modelsim directory. Look for designname.vo.
You'll also find the SDF (delay file) in that directory; it's called
designname_v.sdo.

Back to modelsim. Add the .vo file to your project, and compile it.
[You may have to go in and edit out the line: initial
$sdf_annotate("designname_v.sdo"); ModelSim complains about it) Then
edit the simulation configuration and tell it to use designname_v.sdo
with your chip design. I like to set all of the delays to MAX (I've
been bitten by back-annotated simulations using "typical" delays.)

Like I said, I'm sure that Altera's documention can tell you how to do
this.

-a

 

[ALuPin]

Hi,

thank you about your reply.

But what about .vho file. What is this file for?

Rgds

Bassman59a@yahoo.com (Andy Peters) wrote in message news:<9a2c3a75.0405101246.38545bef@posting.google.com>...

ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0405100255.9edda8b@posting.google.com>...
Hi newsgroup people,

I want to perform a timing simulation of an SRAM controller with
Modelsim (version Altera 5.7e)

I am working with Altera QuartusII software (version 4.0 SP1).

For the purpose of a timing simulation under Modelsim I would like to
know how to make settings in QuartusII to get the correct output files
and how to include them in Modelsim.

I'm sure this is all documented somewhere, so it's clearly time to
RTFM.

Basically, the fitter spits out a Verilog or VHDL model of your
design. This model has the port interface, but the innards are
replaced with the particular FPGA's low-level features and the proper
interconnects. By default, Quartus puts this file in the
design_root>\simulation\modelsim directory. Look for designname.vo.
You'll also find the SDF (delay file) in that directory; it's called
designname_v.sdo.

Back to modelsim. Add the .vo file to your project, and compile it.
[You may have to go in and edit out the line: initial
$sdf_annotate("designname_v.sdo"); ModelSim complains about it) Then
edit the simulation configuration and tell it to use designname_v.sdo
with your chip design. I like to set all of the delays to MAX (I've
been bitten by back-annotated simulations using "typical" delays.)

Like I said, I'm sure that Altera's documention can tell you how to do
this.

-a