how to parameterized my design

[friend.05@gmail.com]

Hi,

I want to implement the following expression. But depending on number
input expression becomes wider.


2 input:

assign g32 = gblock16[1] | (gblock16[0] & pblock16[1]);
assign p32 = pblock16[0] & pblock16[1];

3 input:

assign g40 = gblock8[2] | (gblock16[1] & pblock8[2]) | (gblock16[0] &
pblock16[1] & pblock8[2]);

assign p40 = pblock16[0] & pblock16[1] & pblock8[2];


4 input :

assign g56 = gblock8[3] | (gblock16[2] & pblock8[3]) | (gblock16[1] &
pblock16[2] & pblock8[3]) | (gblock16[0] & pblock16[1] & pblock16[2] &
pblock8[3] );

assign p56 = pblock16[0] & pblock16[1] & pblock16[2] & pblock8[3];


I want implement this expression using verilog.

How to implement generalisd design (parameterised design) for such
expression.

 

[Michael]

Give the formula

 

Looks like standard generate-propagate logic for carry lookahead.