How to not get a flop from synthesis

[googler]

Let us say we have a module definition like this.

module mymod(out1, out2, out3, out4, in1, in2, in3);
output out1;
output out2;
output out3;
output out4;
input in1;
input in2;
input in3;

wire out1;
reg out2, out3, out4;
wire in1, in2, in3;
.....
.....
endmodule

Now because of a change in the design, I don't need the outputs out2,
out3 and out4 any more. I do not want to change the module interface
(as that would involve a lot of work), but it will suffice if I send
0's on the output ports out2, out3 and out4. Now since these ports are
non-functional, I don't want the synthesis tool to create a flop
corresponding to each of out2, out3 and out4 so that I can save some
area. Each of these outputs are being assigned to inside an always
block, like..
always @(blah1 blah1)
begin
....
out2 <= blah2 blah2;
....
end

In the above code, if I replace "blah2 blah2" with 0, will it still
synthesize out2 as a flop? If yes, then how can I not get a flop for
out2? Perhaps declaring out2 as type "wire" and assigning it to 0 in a
continuous assignment statement (outside the always block)?

Thanks for any help.

 

[John_H]

googler wrote:

Let us say we have a module definition like this.

module mymod(out1, out2, out3, out4, in1, in2, in3);
output out1;
output out2;
output out3;
output out4;
input in1;
input in2;
input in3;

wire out1;
reg out2, out3, out4;
wire in1, in2, in3;
....
....
endmodule

Now because of a change in the design, I don't need the outputs out2,
out3 and out4 any more. I do not want to change the module interface
(as that would involve a lot of work), but it will suffice if I send
0's on the output ports out2, out3 and out4. Now since these ports are
non-functional, I don't want the synthesis tool to create a flop
corresponding to each of out2, out3 and out4 so that I can save some
area. Each of these outputs are being assigned to inside an always
block, like..
always @(blah1 blah1)
begin
....
out2 <= blah2 blah2;
....
end

In the above code, if I replace "blah2 blah2" with 0, will it still
synthesize out2 as a flop? If yes, then how can I not get a flop for
out2? Perhaps declaring out2 as type "wire" and assigning it to 0 in a
continuous assignment statement (outside the always block)?

Thanks for any help.

Which synthesizer? Many will optimize to the equivalent of

wire out2, out3, out4;
assign out2 = 1'b0;
assign out3 = 1'b0;
assign out4 = 1'b0;

but it mey be compiler dependent. SynplifyPro, for instance, will
easily give you the optimized wire unless you force it to keep the reg
with a directive.

- John_H

 

[googler]

On Dec 13, 7:51 pm, John_H <newsgr...@johnhandwork.com> wrote:

googler wrote:
[snip]
always @(blah1 blah1)
begin
....
out2 <= blah2 blah2;
....
end

In the above code, if I replace "blah2 blah2" with 0, will it still
synthesize out2 as a flop? If yes, then how can I not get a flop for
out2? Perhaps declaring out2 as type "wire" and assigning it to 0 in a
continuous assignment statement (outside the always block)?

Thanks for any help.

Which synthesizer? Many will optimize to the equivalent of

wire out2, out3, out4;
assign out2 = 1'b0;
assign out3 = 1'b0;
assign out4 = 1'b0;

but it mey be compiler dependent. SynplifyPro, for instance, will
easily give you the optimized wire unless you force it to keep the reg
with a directive.

I am using magma for synthesis. Will it be any different?