How To multiplex an external bus

I am very new to FPGAs, so please bear with me..

I have an 8 bit wide bus (+4 various control signals) that are going
into my FPGA. I'd like to conditionally connect
ths external bus to another external bus with the same specs. The
goal is so that the devices on the first bus
see the devices on the second bus (and vice-versa), but internally I
can disconnect it when prompted so that
devices on both busses only see me (the fpga) but not whats on the
other bus.

Is this a plausible scheme? Can it be accomplished with just a simple
multiplexer?

 

[Rob]

Yes, this is plausible. Give us some detail about the bus specifications:
voltage levels, speeds, etc... You might get a way with a CPLD, which are
perfect for combinatorial tasks--like a mux. One nice feature of a CPLD is
its deterministic Tpd (propagation delays) through the device. So, in your
case, skew will be kept tight between the 8 bit wide bus.

I recently did a very similar design and used a CPLD. I had two16 bit input
busses that I was muxing onto one 16 bit output bus. My signals were LVTTL
running @ 66MHz--easy for today's CPLD's.




<benn686@hotmail.com> wrote in message
news:1185570177.833511.146430@z24g2000prh.googlegroups.com...

I am very new to FPGAs, so please bear with me..

I have an 8 bit wide bus (+4 various control signals) that are going
into my FPGA. I'd like to conditionally connect
ths external bus to another external bus with the same specs. The
goal is so that the devices on the first bus
see the devices on the second bus (and vice-versa), but internally I
can disconnect it when prompted so that
devices on both busses only see me (the fpga) but not whats on the
other bus.

Is this a plausible scheme? Can it be accomplished with just a simple
multiplexer?

 

The bus is 3.3v, 1Mhz. I put the mux on the top level file, all the
signals below come into the FPGA, except for the signals xxx_internal,
which come from a sub-module. Basically I want to connect the
external signals together depending on sel, or have the SN_ signals
connected from a sub-module:


// Tx
assign SN_Tx_inh_A = sel ? SN_Tx_inh_A_internal :
FS_Tx_inh_A ;
assign SN_Tx_A = sel ? SN_Tx_A_internal : FS_Tx_A;
assign SN_Tx_A_N = sel ? SN_Tx_A_N_internal :
FS_Tx_A_N ;
assign SN_Tx_inh_B = sel ? SN_Tx_inh_B_internal :
FS_Tx_inh_B ;
assign SN_Tx_B = sel ? SN_Tx_B_internal : FS_Tx_B;
assign SN_Tx_B_N = sel ? SN_Tx_B_N_internal :
FS_Tx_B_N ;

// Rx
assign SN_Rx_A_internal = sel ? SN_Rx_A : FS_Rx_A;
assign SN_Rx_A_N_internal = sel ? SN_Rx_A_N : FS_Rx_A_N;
assign SN_Rx_B_internal = sel ? SN_Rx_B : FS_Rx_B ;
assign SN_Rx_B_N_internal = sel ? SN_Rx_B_N : FS_Rx_B_N;

The 'sel' signal comes from a sub module that decides whether to
connect the second bus (SN) to the first bus (FS). I've even tried
hardcoding it without the select, i.e.
assign SN_Tx_A = FS_Tx_A;
yet, I still dont see any activity on the second bus. Can signals
like this be assigned without using 'always'?

 

[Rob]

Yes, you can use the assign command without an always construct.
Your hardwire command "assign SN_Tx_A = FS_Tx_A;" is valid and
should tie those two pins directly together. What device/tools are you
using for this design? I would look through the synthesis report for some
clues. An RTL view of your design might offer some direction as well.


<benn686@hotmail.com> wrote in message
news:1185837409.349011.300940@x40g2000prg.googlegroups.com...

The bus is 3.3v, 1Mhz. I put the mux on the top level file, all the
signals below come into the FPGA, except for the signals xxx_internal,
which come from a sub-module. Basically I want to connect the
external signals together depending on sel, or have the SN_ signals
connected from a sub-module:


// Tx
assign SN_Tx_inh_A = sel ? SN_Tx_inh_A_internal :
FS_Tx_inh_A ;
assign SN_Tx_A = sel ? SN_Tx_A_internal : FS_Tx_A;
assign SN_Tx_A_N = sel ? SN_Tx_A_N_internal :
FS_Tx_A_N ;
assign SN_Tx_inh_B = sel ? SN_Tx_inh_B_internal :
FS_Tx_inh_B ;
assign SN_Tx_B = sel ? SN_Tx_B_internal : FS_Tx_B;
assign SN_Tx_B_N = sel ? SN_Tx_B_N_internal :
FS_Tx_B_N ;

// Rx
assign SN_Rx_A_internal = sel ? SN_Rx_A : FS_Rx_A;
assign SN_Rx_A_N_internal = sel ? SN_Rx_A_N : FS_Rx_A_N;
assign SN_Rx_B_internal = sel ? SN_Rx_B : FS_Rx_B ;
assign SN_Rx_B_N_internal = sel ? SN_Rx_B_N : FS_Rx_B_N;

The 'sel' signal comes from a sub module that decides whether to
connect the second bus (SN) to the first bus (FS). I've even tried
hardcoding it without the select, i.e.
assign SN_Tx_A = FS_Tx_A;
yet, I still dont see any activity on the second bus. Can signals
like this be assigned without using 'always'?