How to model an internal state in a function (or a procedure

[fl]

Hi,

After I get helps from several on-line groups, I can calculate a CRC with a VHDL
project. The problem now is that I can get the 16-bit checksum in one time
calculation. Some real FPGA implementations use 8-bit. Thus, I guess that it needs
two clocks to get a 16-bit CRC checksum. My code originates from a function call,
which is a combination logic (no register), from on-line post. When I modify it to
get 8-bit one time for a 16-bit CRC checksum, I find that I have to store the
internal states for the next iterative CRC calculation (Is this right?)
The function call seems not work in this way (It only output the result, not the
internal states). The CRC problem is just like an integer division. I have to
store the residue and the new divisor (dividend is polynomial, constant in this
case). It looks like the residue must have attribute of 'in' and 'out'. In both
function and procedure, parameters can be set to 'in', 'out' or 'inout'.

I am new to VHDL function/procedure. They do not look like easy. Could you express
your idea to help me? Thanks,

 

[rickman]

On 8/5/2014 5:01 PM, fl wrote:

Hi,

After I get helps from several on-line groups, I can calculate a CRC with a VHDL
project. The problem now is that I can get the 16-bit checksum in one time
calculation. Some real FPGA implementations use 8-bit. Thus, I guess that it needs
two clocks to get a 16-bit CRC checksum. My code originates from a function call,
which is a combination logic (no register), from on-line post. When I modify it to
get 8-bit one time for a 16-bit CRC checksum, I find that I have to store the
internal states for the next iterative CRC calculation (Is this right?)
The function call seems not work in this way (It only output the result, not the
internal states). The CRC problem is just like an integer division. I have to
store the residue and the new divisor (dividend is polynomial, constant in this
case). It looks like the residue must have attribute of 'in' and 'out'. In both
function and procedure, parameters can be set to 'in', 'out' or 'inout'.

I am new to VHDL function/procedure. They do not look like easy. Could you express
your idea to help me? Thanks,

Are you new to HDL in general? HDL means Hardware Description Language.
There are no small number of designers who use HDL as a language and
don't bother considering what hardware will be produced which can work
perfectly well. In this case I think looking at what hardware you wish
to produce will do you wonders.

A CRC is not a complex function. It is just a register and a few
exclusive or gates (XOR). The only trick is knowing what to connect to
what with the XOR gates. Your function can be written to describe the
XOR gates and be purely combinatorial. Then you can connect it to your
inputs and a register and Bob's your uncle!

Try starting with a very simple CRC that you have example data for
testing. It will be much easier to see what is happening.

--

Rick

 

[Andy]

I use a procedure with an inout variable parameter for the CRC value, and an in parameter for the data to be CRC'd (bit, byte, word, block, etc.)

Just initialize the crc variable once, and then call the procecure with (data, crc) each time you get new data, and it will update the crc variable each time.

Because it can be written to accept an entire block of data (unconstrained array of bytes), such a procedure can be very useful in testbenches too.

Andy