How to mix verilog and vhdl files in one core

[Jelmer]

Our first goal was translating verilog files to vhdl files.

Now we want to do a fault detection by mixing both verilog and vhdl
files.

for example:

we have: name_1.v, name_2.v, name_3.v and name_1.vhd, name_2.vhd,
name_3.vhd

the core with the verilog files works, the core with the vhd files
doesn't.

We want to test the separate files by combining those two languages:

name_1.v; name_2.vhd; name_3.vhd

Is this possible?

 

[JuanC]

This is possible, I just finished implementing a similar thing. I
instantiated verilog modules in my vhdl; you have to be exact in your
syntax as the verilog/vhdl boundary has to be handled with care. You
will have to create a wrapper in vhdl for your verilog module such as
below:

-- VHDL module (name_1_mixed.vhd)
entity name_1_mixed is
generic (
WIDTH : integer := 4
);
port (
dataOut : out std_logic_vector(WIDTH-1 downto 0);
clk : in std_logic;
rst : in std_logic
);
end name_1_mixed;

architecture verilog of name_1_mixed is
component name_1 --(This component name must match the verilog module)
generic (
WIDTH : integer :=4);
port (
dataOut : out std_logic_vector(WIDTH-1 downto 0);
clk : in std_logic_vector;
rst : in std_logic_vector);
end component;
begin
u_verilog : name_1
generic map (
WIDTH)
port map (
dataOut -- Port names must match exactly
clk -- I've found you can only pass by location
rst); -- and only std_logic and std_logic_vectors
end architecture;

// Verilog module (name_1.v)
module name_1
#(parameter
WIDTH = 4)
(
output reg [WIDTH-1:0] dataOut,
input clk,
input rst
);
// module contents
endmodule


Hope this helps!

 

[KJ]

On Feb 15, 11:19 am, "JuanC" <juan.javier.cuel...@gmail.com> wrote:

This is possible, I just finished implementing a similar thing. I
instantiated verilog modules in my vhdl; you have to be exact in your
syntax as the verilog/vhdl boundary has to be handled with care. You

Or to put it more simply, just instantiate the Verilog module in your
VHDL code in the exact same manner as if you were instantiating a VHDL
entity...no different.

Kevin Jennings

 

[Mark McDougall]

JuanC wrote:

You
will have to create a wrapper in vhdl for your verilog module such as
below:

Not true at all. In fact, all you've done is pushed the instantiation of
verilog module down 1 level - there's no reason you can't instantiate it
at the top level. You just need a VHDL component declaration for it.

clk -- I've found you can only pass by location

Not true again, you can pass by name as well.

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[KJ]

You just need a VHDL component declaration for it.

You don't need the VHDL component declaration either, just use direct entity
instantation...only use component declarations where you have a black box.

i.e.

The_Verilog_Module : entity work.My_Verilog_Module port map(....)

Kevin Jennings

 

[Pieter]

On 16 feb, 12:53, "KJ" <kkjenni...@sbcglobal.net> wrote:

You just need a VHDL component declaration for it.

You don't need the VHDL component declaration either, just use direct entity
instantation...only use component declarations where you have a black box.

i.e.

The_Verilog_Module : entity work.My_Verilog_Module port map(....)

Kevin Jennings
We forgot to mention that in ISE all works fine, but if we want to mix

in EDK the program still looks for as well the verilog as the vhdl
files.
We can edit the mpd file, and write mixed or, vhdl or verilog, but
when downloading the bitstream EDK still asks for all the files
We must use EDK because we also use headers and sources in our program.