How to make this mux synthesizable?

[Verictor]

Hi,

Given this model:

module finout(a, b, s, z);
input a;
inout b;
input s;
inout z;


assign z = (s) ? a : b;

endmodule

This can't be synthesized because z is an inout while a and b are not
the same type. Is there a way to have a synthesizable implementation?

Thanks.

 

[gabor]

On Mar 30, 1:22 pm, "Verictor" <stehu...@gmail.com> wrote:

Hi,

Given this model:

module finout(a, b, s, z);
input a;
inout b;
input s;
inout z;

assign z = (s) ? a : b;

endmodule

This can't be synthesized because z is an inout while a and b are not
the same type. Is there a way to have a synthesizable implementation?

Thanks.

I seem to be able to synthesize this code. Also why do you say a and
b
are not the same type. Since they are not defined otherwise, they
should
both be scalar wires. What program are you using for synthesis?
What's
your target device? Perhaps the device itself has a restriction on
feedback
of output signals (there's mo assignment to b in your snippet, but I'm
assuming it was declared inout for a reason).

 

[Verictor]

On Mar 30, 12:39 pm, "gabor" <g...@alacron.com> wrote:

On Mar 30, 1:22 pm, "Verictor" <stehu...@gmail.com> wrote:





Hi,

Given this model:

module finout(a, b, s, z);
input a;
inout b;
input s;
inout z;

assign z = (s) ? a : b;

endmodule

This can't be synthesized because z is an inout while a and b are not
the same type. Is there a way to have a synthesizable implementation?

Thanks.

I seem to be able to synthesize this code. Also why do you say a and
b
are not the same type. Since they are not defined otherwise, they
should
both be scalar wires. What program are you using for synthesis?
What's
your target device? Perhaps the device itself has a restriction on
feedback
of output signals (there's mo assignment to b in your snippet, but I'm
assuming it was declared inout for a reason).- Hide quoted text -

- Show quoted text -

It can be synthesized but z has non three-state driver. I basically
want to mux out a and b. But obviously mux won't work because b is an
inout net type as well as z. For example, when input comes from z and
tries to reach b through the mux.

Yes, b has to be declared as inout for other reasons not shown on my
example.

 

[John_H]

"Verictor" <stehuang@gmail.com> wrote in message
news:1175281434.025290.309980@n59g2000hsh.googlegroups.com...

It can be synthesized but z has non three-state driver. I basically
want to mux out a and b. But obviously mux won't work because b is an
inout net type as well as z. For example, when input comes from z and
tries to reach b through the mux.

Yes, b has to be declared as inout for other reasons not shown on my
example.

Is your problem that you want b and z to be connected bidirectionally?
Are you getting valid results for z in all cases but not for b?

Otherwise, I miss the obviousness of why the "mux won't work."

 

[Verictor]

On Mar 30, 2:40 pm, "John_H" <newsgr...@johnhandwork.com> wrote:

"Verictor" <stehu...@gmail.com> wrote in message

news:1175281434.025290.309980@n59g2000hsh.googlegroups.com...



It can be synthesized but z has non three-state driver. I basically
want to mux out a and b. But obviously mux won't work because b is an
inout net type as well as z. For example, when input comes from z and
tries to reach b through the mux.

Yes, b has to be declared as inout for other reasons not shown on my
example.

Is your problem that you want b and z to be connected bidirectionally?
Are you getting valid results for z in all cases but not for b?

Otherwise, I miss the obviousness of why the "mux won't work."

Yes, the problem is that b and z wanted to be connected
bidirectionally. A mux can't be bidirectional. I didn't simulate the
module for b and z in all cases but I think the module won't work due
to uni-directional feature of mux.

Thanks though.

 

[John_H]

Verictor wrote:

Hi,

Given this model:

module finout(a, b, s, z);
input a;
inout b;
input s;
inout z;


assign z = (s) ? a : b;

assign b = s ? 1'bz : z; // Bidirectional z,b

endmodule

This can't be synthesized because z is an inout while a and b are not
the same type. Is there a way to have a synthesizable implementation?

Thanks.

 

[Jonathan Bromley]

On 31 Mar 2007 13:50:48 -0700, "Verictor" <stehuang@gmail.com> wrote:

Yes, the problem is that b and z wanted to be connected
bidirectionally. A mux can't be bidirectional. I didn't simulate the
module for b and z in all cases but I think the module won't work due
to uni-directional feature of mux.

I suspect that you can't build what you want unless you
use pass switches in hardware.

That's easy to model in Verilog, but I don't think any
synthesis tools can do it:

module finout(input a, inout b, input s, inout z);
tranif0 pass_b (z, b, s);
bufif1 drive_a (z, a, s);
endmodule

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Jonathan Bromley, Consultant

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