How to make assign with large delay?

[Patrick Phung]

Hi,

I have this statement and the signal I pulses for 5 time units.
The O does not toggle because the 5 is less than 10.

assign #(10) O = I;

Is there anyway to make an assignment in Verilog so that I will
propagate to O even though the signal width is less than the delay?

Thanks.

Patrick

 

[David Rogoff]

Patrick Phung <patrick.phung@xilinx.com> writes:

Hi,

I have this statement and the signal I pulses for 5 time units.
The O does not toggle because the 5 is less than 10.

assign #(10) O = I;

Is there anyway to make an assignment in Verilog so that I will
propagate to O even though the signal width is less than the delay?

It's the old inertial vs transport delay problem. I'm suprised this
hasn't come up again more recently.

reg O; // must declare as reg, not wire

always @(I)
O <= #(10) I; // must use non-blocking assign

 

[Jonathan Bromley]

"Patrick Phung" <patrick.phung@xilinx.com> wrote in
message news:3FA03C82.B6115055@xilinx.com...

I have this statement and the signal I pulses for 5 time units.
The O does not toggle because the 5 is less than 10.

assign #(10) O = I;

Is there anyway to make an assignment in Verilog so that I will
propagate to O even though the signal width is less than the delay?

Continuous assignment uses inertial delay.

To get transport delay (pure time delay) try using
intra-assignment delay in nonblocking assignments:

reg O;
always @(I) O <= #10 I;

HTH
--
Jonathan Bromley, Consultant

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