A
Attila Csosz
Guest
Hi,
How to make a simple "gateway" in vhdl?
It has two port ( d and q ). When d receives a new value it must transfer to
q. And when q receives a new values it must transfer to d. It should avoid
self triggering.
I tried this but this is maybe not a good solution. For example self
triggering..?
ENTITY comp IS
PORT (d : INOUT std_logic;
q : INOUT std_logic
);
END comp;
ARCHITECTURE arch OF comp IS
BEGIN
comp_process1: PROCESS (d)
BEGIN
q <= d;
END PROCESS;
comp_process2: PROCESS (q)
BEGIN
d <= q;
END PROCESS;
END arch;
Thanks
Attila
How to make a simple "gateway" in vhdl?
It has two port ( d and q ). When d receives a new value it must transfer to
q. And when q receives a new values it must transfer to d. It should avoid
self triggering.
I tried this but this is maybe not a good solution. For example self
triggering..?
ENTITY comp IS
PORT (d : INOUT std_logic;
q : INOUT std_logic
);
END comp;
ARCHITECTURE arch OF comp IS
BEGIN
comp_process1: PROCESS (d)
BEGIN
q <= d;
END PROCESS;
comp_process2: PROCESS (q)
BEGIN
d <= q;
END PROCESS;
END arch;
Thanks
Attila