How to make a module only with a fundtion

[thomasc]

Hi all,

I've seen a verilog file(.v) which contains only a function, not even
"module" keyword and parenthesized port list. And the function was called
from another module(another verolog file) in the same project. I tried the
same operation in my project and the files compiled without an error.
However, when I tried to simulate it with a testbench, NodelSim gave an
error message saying "Unresolved reference". (I copied the entire error
message at the bottom.)

I want to find out if I need to do something special in order to call a
function which is specified in another .v file, which consists of only the
function.

Please let me know how I can make this work.
Thank you!

thomasc

==========

# Loading work.test_exp_table
# ** Error: (vsim-3043)
D:/My_Projects/ModelSim/RS_CODEC_byte/benches/test_exp_table.v(14):
Unresolved reference to 'exp_table'.
# Region: /test_exp_table
# ** Error: (vsim-3043)
D:/My_Projects/ModelSim/RS_CODEC_byte/benches/test_exp_table.v(14):
Unresolved reference to 'exp_table' in exp_table.exp_table.
# Region: /test_exp_table
# ** Error: (vsim-3043)
D:/My_Projects/ModelSim/RS_CODEC_byte/benches/test_exp_table.v(14):
Unresolved reference to 'exp_table' in exp_table.$0.
# Region: /test_exp_table
# Error loading design

 

[Jim Wu]

"thomasc" <altecsplinter@hotmail.com> wrote in message
news:aca3622b68f86212197064af78f3de07@localhost.talkaboutprogramming.com...

Hi all,

I've seen a verilog file(.v) which contains only a function, not even
"module" keyword and parenthesized port list. And the function was called
from another module(another verolog file) in the same project. I tried the
same operation in my project and the files compiled without an error.
However, when I tried to simulate it with a testbench, NodelSim gave an
error message saying "Unresolved reference". (I copied the entire error
message at the bottom.)

I want to find out if I need to do something special in order to call a
function which is specified in another .v file, which consists of only the
function.

"`include" the .v file that defines the function in the module that calls
the funtion.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips

 

thomasc wrote:

Hi all,

I've seen a verilog file(.v) which contains only a function, not even
"module" keyword and parenthesized port list. And the function was
called
from another module(another verolog file) in the same project. I
tried the
same operation in my project and the files compiled without an error.
However, when I tried to simulate it with a testbench, NodelSim gave
an
error message saying "Unresolved reference". (I copied the entire
error
message at the bottom.)

I want to find out if I need to do something special in order to call
a
function which is specified in another .v file, which consists of
only the
function.

You need to instantiate your module in the higher-level code, and then
refer to the instance when using the function. For example, given:

module funcmod;
function foo;
begin : functionfoo
...
end // functionfoo
endfuncion
endmodule // funcmod

module testfunc;
// instantiate the module:
funcmod f;

// use the function:
initial begin : useit
f.foo;
end // useit
endmodule // testfunc

hope this helps,
-a
-------------------------------
andy peters
tucson, az