How to make a loop correctly?

[Ilkka Pajari]

Hello.

I'm quite noobie with VHDL and I'm trying to make a delay procedure.
Could someone tell me what's the most reasonable way to make at least
~13 clock cycles delay inside procedure. Maybe I'm thinking too much
about C, because none of my tries haven't been succeeded yet. Here is
one what I have tried so far:

(Procedure is inside clocked process)

procedure delay_s is begin
while (counter < 12) loop
..
..
counter <= counter + 1;
end loop;
counter <= '0';
end procedure delay_s;

What's wrong with procedure above, because loop is infinite?


- Ilkka Pajari

 

[lishen]

which type is your signal counter? std_ulogic/logic or integer???

"Ilkka Pajari" <ipajari@lut.fi> wrote in message
news:d89dhd$plu$1@juuri.cc.lut.fi...

Hello.

I'm quite noobie with VHDL and I'm trying to make a delay procedure. Could
someone tell me what's the most reasonable way to make at least ~13 clock
cycles delay inside procedure. Maybe I'm thinking too much about C,
because none of my tries haven't been succeeded yet. Here is one what I
have tried so far:

(Procedure is inside clocked process)

procedure delay_s is begin
while (counter < 12) loop
..
..
counter <= counter + 1;
end loop;
counter <= '0';
end procedure delay_s;

What's wrong with procedure above, because loop is infinite?


- Ilkka Pajari

 

[Mike Treseler]

Ilkka Pajari wrote:

(Procedure is inside clocked process)

procedure delay_s is begin
while (counter < 12) loop
..
..
counter <= counter + 1;
end loop;
counter <= '0';
end procedure delay_s;

What's wrong with procedure above, because loop is infinite?

The loop never exits because the
value of counter never changes
because signals only update at
the end of a process
(normally at the next rising edge clk)

You don't need a while loop.
Your base process loops automatically
every clock.
Have the procedure call check for
the terminal value. The calling
process does the waiting.

A while loop can't make a delay
because it runs in zero time.

-- Mike Treseler

 

[Ilkka Pajari]

Ok, thanks for the answers. I was trying to do a loop, because in one
architecture writing to the register lasts approximately 13 clock
cycles. During the writing trig-signals must be set high. The wait
statement inside procedure doesn't work, because wait-statements are not
allowed inside procedure.

Counter was type constant. Doesn't it update immediately? I have one
solution to my problem, but it's quite tricky. It's something like this:

SOME_PROCESS:
process(clk, rst)
begin
if clk'event and clk = '1' then
.
.
if signal trig_s is high ==> trig_s <= '0';
.
. (do something here)
.
trig_s <= '1';
.
.
end process;

TRIG_PROCESS:
process(clk, rst, trig_s)
begin
if clk'event and clk = '1' then
if trig_s = '1' or counter > 0 then
if counter < 12 then
reg_updated(#) <= '1';
trig <= '1';
elsif counter = 12 then
reg_updated(#) <= '0';
trig <= '0';
counter <= 0;
end if;
end if;
end if;

end process;



The method above is working, but not very usable when there is many
devices that are connected to the project I'm working with. A procedure
call would be much simplier, but is it even possible to implement in
this case?

- Ilkka Pajari



Mike Treseler wrote:

Ilkka Pajari wrote:

(Procedure is inside clocked process)

procedure delay_s is begin
while (counter < 12) loop
..
..
counter <= counter + 1;
end loop;
counter <= '0';
end procedure delay_s;

What's wrong with procedure above, because loop is infinite?


The loop never exits because the
value of counter never changes
because signals only update at
the end of a process
(normally at the next rising edge clk)

You don't need a while loop.
Your base process loops automatically
every clock.
Have the procedure call check for
the terminal value. The calling
process does the waiting.

A while loop can't make a delay
because it runs in zero time.

-- Mike Treseler

 

signal Clk : std_logic;
....
process
procedure delay_clk is
begin
for i in 0 to 12 loop
wait until rising_edge(Clk);
end loop;
end delay_clk;

begin

delay_clk;

wait;
end process;

What are you going to try ?

Rgds
André