How to make a cap like a cap in pdk?

[YUAN Shuai]

I would like to make my own M1-M2 plate capacitor that could be
parameterized.
Cadence has a sample pcell example of making parameterized layout.
however, I also want to make symbols for the cap and the symbol will
be used in the schematic. And some questions are:
1. how to enable LVS of the symbol in schematic and the pcell layout?
2. how to build the model of the layout pcell so the
simulator(Spectre) can link the symbol with my own cap model?

Thanks!

 

[Andrew Beckett]

YUAN Shuai wrote, on 03/23/11 12:51:

I would like to make my own M1-M2 plate capacitor that could be
parameterized.
Cadence has a sample pcell example of making parameterized layout.
however, I also want to make symbols for the cap and the symbol will
be used in the schematic. And some questions are:
1. how to enable LVS of the symbol in schematic and the pcell layout?
2. how to build the model of the layout pcell so the
simulator(Spectre) can link the symbol with my own cap model?

Thanks!

You might want to take a look at
http://support.cadence.com/wps/mypoc/cos?uri=deeplinkminocumentViewer;src=dt;q=cic_pdks/PRD_Methodology_Guide_version_2.pdf

Regards,

Andrew.