how to list sequential elements in logic cone of a flop.

Hello,

I wish to know, if there is a way I can list out all flip flops (or
latches) which are in the logical cone of another flip flop.

Can this be done using a PLI or some simple perl script, that can be
integrated with verilog compiler such as vcs?

Thanks in advance
Aarul

 

[Ajeetha]

Aarul,
Is this a gate level design? If so, PLI *may be* an option - by
walking through VPI port conenctions, but IMHO - a big pain to do. What
exactly are you trying to do? Why do you need this information?

VCS's GUI - DVE - can extract this for you via its fanin feature from
so called "Path Schematic", not sure if you can filter FFs alone - you
may want to play with that.

Regards
Ajeetha, CVC
www.noveldv.com

aaruljain@gmail.com wrote:

Hello,

I wish to know, if there is a way I can list out all flip flops (or
latches) which are in the logical cone of another flip flop.

Can this be done using a PLI or some simple perl script, that can be
integrated with verilog compiler such as vcs?

Thanks in advance
Aarul

 

[naren]

Hi,
Pls refer to http://www.asic-world.com/verilog/pli3.html . There are
path routines which could be used for your purpose. But I doubt wether
you could querry wether the cell is a sequential cell or not! If your
asic vendor has a unique naming convention, then I think you'll be able
to find it.
Alternatively you could get the information from DC / PT - store it
in a file. If you need the info during simulation, open & process it
during simulation. Postprocess is always advisable. Hence try dumping
out the simulation info as well to a file.
HTH
Naren.
TooMuch Semiconductor Solutions
Bangalore Based VLSI Verification Service & Solutions provider.
www.toomuchsemi.com


aaruljain@gmail.com wrote:

Hello,

I wish to know, if there is a way I can list out all flip flops (or
latches) which are in the logical cone of another flip flop.

Can this be done using a PLI or some simple perl script, that can be
integrated with verilog compiler such as vcs?

Thanks in advance
Aarul

 

THank You for the reply. I think using DC/PT to generate list of cells
and then processing it is ok with me.

naren wrote:

Hi,
Pls refer to http://www.asic-world.com/verilog/pli3.html . There are
path routines which could be used for your purpose. But I doubt wether
you could querry wether the cell is a sequential cell or not! If your
asic vendor has a unique naming convention, then I think you'll be able
to find it.
Alternatively you could get the information from DC / PT - store it
in a file. If you need the info during simulation, open & process it
during simulation. Postprocess is always advisable. Hence try dumping
out the simulation info as well to a file.
HTH
Naren.
TooMuch Semiconductor Solutions
Bangalore Based VLSI Verification Service & Solutions provider.
www.toomuchsemi.com


aaruljain@gmail.com wrote:
Hello,

I wish to know, if there is a way I can list out all flip flops (or
latches) which are in the logical cone of another flip flop.

Can this be done using a PLI or some simple perl script, that can be
integrated with verilog compiler such as vcs?

Thanks in advance
Aarul