How to keep iSE from grounding pins

[Jon Elson]

I have an interface project using XC9500XL CPLDs, using iSE 10.1,
and it grounds all pins that don't have logic connected to them.
I have a couple pins connected to external busses, so they do not
need to be held to prevent floating voltages. I see in the pin report
that they have been grounded with the "PGND" setting. Is there a way in
the UCF file or other way to prevent these several pins from getting the
PGND option? I'd want other unused pins to still be treated that way,
but these pins are wired on the board for future expansion, but are
now jamming bus signals.

This is a one-page VHDL project.

Thanks,

Jon

 

[Jon Elson]

On 02/23/2011 04:59 PM, Jon Elson wrote:

I have an interface project using XC9500XL CPLDs, using iSE 10.1,
and it grounds all pins that don't have logic connected to them.
I have a couple pins connected to external busses, so they do not
need to be held to prevent floating voltages. I see in the pin report
that they have been grounded with the "PGND" setting. Is there a way in
the UCF file or other way to prevent these several pins from getting the
PGND option? I'd want other unused pins to still be treated that way,
but these pins are wired on the board for future expansion, but are
now jamming bus signals.

This is a one-page VHDL project.

Hah, didn't think I'd be able to find this one myself! In implement,

right click, click properties menu, click fitting, and there's an option
"preserve unused inputs". I turned that on, and ONLY the ports listed
in the VHDL port list were kept as inputs, all pins not mentioned there
were set to PGND. That's what I wanted to do, but I couldn't find
ANYTHING in Xilinx's documentation or the forum that mentioned this option.

Jon

 

[glen herrmannsfeldt]

Jon Elson <jmelson@wustl.edu> wrote:

I have an interface project using XC9500XL CPLDs, using iSE 10.1,
and it grounds all pins that don't have logic connected to them.
I have a couple pins connected to external busses, so they do not
need to be held to prevent floating voltages.

I suppose you can turn on some option to float them, but you
can also connect them up as tristate outputs with the output
enable wired low.

-- glen

 

[NeedCleverHandle]

On Feb 23, 3:50 pm, Jon Elson <jmel...@wustl.edu> wrote:

 That's what I wanted to do, but I couldn't find
ANYTHING in Xilinx's documentation or the forum that mentioned this option.

Jon

It's out there: <http://www.xilinx.com/support/answers/3404.htm>

You just don't have keys to the ivory tower yet.

RK

 

[Jon Elson]

On 02/25/2011 10:19 AM, NeedCleverHandle wrote:

On Feb 23, 3:50 pm, Jon Elson<jmel...@wustl.edu> wrote:
That's what I wanted to do, but I couldn't find
ANYTHING in Xilinx's documentation or the forum that mentioned this option.

Jon

It's out there:<http://www.xilinx.com/support/answers/3404.htm
No, that tells you how TO ground them, I wanted it to NOT ground several

that were currently unused, but declared in the VHDL port list. That is
the "preserve unused inputs" option, on the same page.

Jon

 

[Gabor]

On Friday, February 25, 2011 3:12:47 PM UTC-5, Jon Elson wrote:

On 02/25/2011 10:19 AM, NeedCleverHandle wrote:
On Feb 23, 3:50 pm, Jon Elson<jme...@wustl.edu> wrote:
That's what I wanted to do, but I couldn't find
ANYTHING in Xilinx's documentation or the forum that mentioned this option.

Jon

It's out there:<http://www.xilinx.com/support/answers/3404.htm
No, that tells you how TO ground them, I wanted it to NOT ground several
that were currently unused, but declared in the VHDL port list. That is
the "preserve unused inputs" option, on the same page.

Jon

It seems a bit backwards for the tools to automatically
ground pins that are unused, and then require you to
specifically include and float pins you DON'T want
grounded. I'm always worried that a pin will be
optimized out of the design and end up frying something
at the other end of the net. My defaults would be to
float unused pins, then specifically create an output
like (Verilog):

parameter PINS_TO_GND = 18;

output [PINS_TO_GND-1:0] grounded_pins;

assign grounded_pins = {PINS_TO_GND{1'b0}};

and then place the pins requiring grounding in the
..ucf file.

On the other hand I usually work with boards that are
already designed when I design the innards of
the programmable logic, so a lot of things about the
Xilinx tools seems backwards. For example I have
to set a special switch to allow unmatched LOC
constraints for pins that are on the board, and
have names, but I don't use in a particular
version of the design. At the same time if I have
an output port in my design WITHOUT a LOC constraint
I get no error or warning. The latter case can
cause havoc on a board where the un-LOCed output
gets assigned to some random pin. As far as I
can see there's no "production" mode for
constraints that would make it an error to
have any un-LOCed IOB's.

-- Gabor