How to introduce delay in Structural description ?

[priya]

Hi all,

The follwing code is simple 2-input and gate model.
Here I am having doubt.


begin
t1 : and4 port map ( in1, in2, out1 );
t2 : and_output port map ( out1,out2);

end and_arch ;


I know these two instance t1,t2 will be executed concurrently at 0 ns
simulation time.But here T1 instance will execute at 0ns simulation
time.t2 instance will execute after updated the value from out1.So Here
I need to introduce some delay to execute the t2 instance at some
simulation time.

How to introduce delay at instance t1? Give me some ideas to proceed
further?

regards,
priya




------------------------------------------------
entity and4 is
port ( in1, in2 : in bit;
out1 : out bit );
end;
architecture only of and4 is
begin
out1<=in1 and in2;
end;
-----------------------------------------
entity and_output is
port ( out1 : in bit;
out2 : out bit
);
end;
architecture out_arch of and_output is
begin
out2<=out1;
end;
-- -- -- -----------------------

library STD;
use STD.TEXTIO.all;
entity testbench is
end testbench;
architecture and_arch of testbench is
component and4
port ( in1, in2 : in bit;
out1 : out bit
);
end component;
component and_output
port ( out1: in bit;
out2: out bit
);
end component;
signal in1 : bit;
signal in2 : bit;
signal out1 : bit;
signal out2 : bit;
begin
t1 : and4 port map ( in1, in2, out1 );
t2 : and_output port map ( out1,out2);

end and_arch ;

 

[Mike Treseler]

priya wrote:

How to introduce delay at instance t1?

If you mean for simulation, delta delays
are already built into the language.

If you mean a synthesized delay, you need
to describe a counter or shift register.

-- Mike Treseler

 

[priya]

Thanks Mike...

I meant it for Simulation Delay.I want to give extra delay for
instance t2 module.

For example In Verilog we can give delay when the module
instantiation

for eg...and #(3) gate1 (out1, in1, in2);

My question is How can we add the delay statement in VHDL while
module instantiation.

 

[Ralf Hildebrandt]

priya wrote:

I meant it for Simulation Delay.I want to give extra delay for
instance t2 module.

For example In Verilog we can give delay when the module
instantiation

for eg...and #(3) gate1 (out1, in1, in2);

My question is How can we add the delay statement in VHDL while
module instantiation.

What about mapping the output to a dummy signal and a wait statement,
that copies the value from the dummy to the real output?

t1 : and4 port map ( in1, in2, outdummy);

process(outdummy)
begin
wait for 1 ns;
out1<=outdummy;
end process;

It introduces a little bit more code, but this should not be a problem,
because modifications have to be done anyway.

Ralf

 

[sudhi]

You could use the AFTER construct
As in
entity and4 is
port ( in1, in2 : in bit;
out1 : out bit );
end;
architecture only of and4 is
begin
out1<=in1 and in2 AFTER 3 ns;
end;

 

[priya]

You could use the AFTER construct
As in
entity and4 is
port ( in1, in2 : in bit;
out1 : out bit );
end;
architecture only of and4 is
begin
out1<=in1 and in2 AFTER 3 ns;
end;


But still the t2 instance will execute at simulation time 0ns without
updated the value from out1.But I dont want to execute that t2 instance
at time 0ns..I want to add some dalay may be 3ns to t2 instance...t2
will execute only at 3 ns not at 0ns ...

How is it possible ....
plz someone answer my question.....

 

[Bill Mills]

priya wrote:

You could use the AFTER construct
As in
entity and4 is
port ( in1, in2 : in bit;
out1 : out bit );
end;
architecture only of and4 is
begin
out1<=in1 and in2 AFTER 3 ns;
end;


But still the t2 instance will execute at simulation time 0ns without
updated the value from out1.But I dont want to execute that t2 instance
at time 0ns..I want to add some dalay may be 3ns to t2 instance...t2
will execute only at 3 ns not at 0ns ...

How is it possible ....
plz someone answer my question.....

All processes execute once at time zero. For simulation, wait until
time > 0 could be used. The wait until statement will be ignored for
systhesis.

 

[Jonathan Bromley]

On 10 Oct 2005 08:40:29 -0700, "Bill Mills" <millswp@yahoo.com> wrote:

All processes execute once at time zero. For simulation, wait until
time > 0 could be used. The wait until statement will be ignored for
systhesis.

WHOOOHOOO, please don't do this.

"wait until" constructs a sensitivity list from every signal
in its expression. The expression NOW > 0 contains no
signals, so there is no sensitivity list and the wait
will hang for ever. The correct recipe is "wait for 1 fs;"
or something equally disgusting.

Note that "wait for 0 ns;" is also meaningful, although it's
not entirely clear that it means what you want it to mean
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Jonathan Bromley]

On 10 Oct 2005 03:56:48 -0700, "priya" <priya11.karthik@gmail.com>
wrote:

But still the t2 instance will execute at simulation time 0ns without
updated the value from out1.But I dont want to execute that t2 instance
at time 0ns..I want to add some dalay may be 3ns to t2 instance...t2
will execute only at 3 ns not at 0ns ...

How is it possible ....
plz someone answer my question.....

I cannot, for the life of me, understand why you are trying to
postpone the execution of the process within t2.

In fact, the code inside t2 probably executes twice at time 0:
once when all the inputs are initialised (to zero, since you are
using bit rather than the more appropriate std_ulogic) and
again one delta cycle later when the output of t1 updates and
propagates to the input of t2. Why is this inappropriate for you?

It is also necessary for you to be clearer in your use of language.
You don't "execute" an instance. All instances are elaborated
(constructed) before simulation begins. A process within an
instance may execute, of course. There is nothing you can do
to stop all processes starting to execute at time zero - that's
the way VHDL is defined to work. However, you *can* pause
processes if you wish. For example, this process is a rather
stupid AND gate model that does nothing for 2ns and then
works normally at all future times. Note that it has no
sensitivity list, but instead uses a "wait on" statement
to control an infinite loop.

process begin
wait for 2 ns;
loop
y <= a and b;
wait on a, b;
end loop;
end process;

Please explain what you mean by "add delay to an instance".
Others have already shown how you can easily model a gate
propagation delay; here's perhaps a nicer way of adding that
to a model...

entity slow_and_gate is
generic (delay: time := 0 ns);
port (a,b: in bit; y: out bit);
end;
architecture behavioural of slow_and_gate is
begin
y <= a and b after delay;
end;

Now, when instantiating this thing, you can configure the
delay by setting the generic... (component declaration
skipped for brevity):

t2: slow_and_gate
generic map (delay => 2 ns)
port map (a => in1, b => in2, y => out1);

SO........................
back to my original question: Why is this (Verilog-like)
behaviour not what you want? What are you trying to model?
And why is it a good idea for a model to be asleep at time 0?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.