How to interpret results of Synplify Pro

[srini]

Hi,
I am new to designing with FPGA's. I am using Synplify Pro 8.4 for
synthesis. I am seeing lot of information in the log file and cudnt get
how to go about interpreting them. I am also not sure of whether I can
giving the correct options for synthesis. How can I make sure I am
synthesising properly witht the correct options, my design runs at the
expected freq. and things like that. what is the "slack time"? Can
anyone help me with some guidelines for getting correct synthesis
results and efficient way of using synthesis tools?

 

[Mike Treseler]

srini wrote:

Can
anyone help me with some guidelines for getting correct synthesis
results and efficient way of using synthesis tools?

Use a synchronous style and specify Fmax.
Run a sim first unless the design is trivial.


-- Mike Treseler

 

[Julien Lochen]

Hello Srini,

Synplify is more easy to use than XST for exemple.

Firstable, specify your clock, it is a key.

Lots of parameters are configurable but use the default values, it will
suit your design for the beginning.

Then have a look on the user guide of Sinplify. In particulary, try to
understand the key-word that you have
to insert in your verilog (or VHDL) to constraint the tools.