F
Fred Ma
Guest
Hello,
My university has NC-verilog from cadence. I've used
it mostly from the command-line, in much the same way I
used verilog-XL.
I have also used matlab/c++ (with the standard template
library, STL) to explore some CAD algorithms. Matlab
is the top-most environment. It calls my C++ program,
which was compiled in a very specifical way (described
in the matlab documentation) to be called as a dynamic
library. My C++ program does call-backs to the parent
matlab environment for some things. Some matlab files
are also used in the compilation process.
I've come to a phase in my thesis where I have to
combine matlab, C++/STL, and nc-verilog. The C++ code
must evaluate a great number of verilog designs by
repeatedly invoking simulations. Hopefully, I can do
this by keeping the simulation engine running and
simply resubmitting various verilog files. Only
certain parameter definitions will change between the
various simulations. Hopefully, I can avoid
recompiling. Ideally, I can extract output data from
certain nodes without having to write to a file.
My understanding is that API work can be very
cumbersome and messy. A colleague suggested looking at
SystemC. He has some experience with Verilog's PLI,
but advises against going that route. So I will start
checking out the SystemC website.
I wonder if more experienced people than I can give me
a heads up on what to expect. Can I still have matlab
as the topmost environment, with my C++ code launching
some verilog environment? I mean cleanly, of course,
though some way is better than no way. Is there an
example/tutorial on this?
Thanks.
Fred
My university has NC-verilog from cadence. I've used
it mostly from the command-line, in much the same way I
used verilog-XL.
I have also used matlab/c++ (with the standard template
library, STL) to explore some CAD algorithms. Matlab
is the top-most environment. It calls my C++ program,
which was compiled in a very specifical way (described
in the matlab documentation) to be called as a dynamic
library. My C++ program does call-backs to the parent
matlab environment for some things. Some matlab files
are also used in the compilation process.
I've come to a phase in my thesis where I have to
combine matlab, C++/STL, and nc-verilog. The C++ code
must evaluate a great number of verilog designs by
repeatedly invoking simulations. Hopefully, I can do
this by keeping the simulation engine running and
simply resubmitting various verilog files. Only
certain parameter definitions will change between the
various simulations. Hopefully, I can avoid
recompiling. Ideally, I can extract output data from
certain nodes without having to write to a file.
My understanding is that API work can be very
cumbersome and messy. A colleague suggested looking at
SystemC. He has some experience with Verilog's PLI,
but advises against going that route. So I will start
checking out the SystemC website.
I wonder if more experienced people than I can give me
a heads up on what to expect. Can I still have matlab
as the topmost environment, with my C++ code launching
some verilog environment? I mean cleanly, of course,
though some way is better than no way. Is there an
example/tutorial on this?
Thanks.
Fred