How to Instantiate RAM & ROM using Verilog HDL in Behavioral

[Peng Yu]

Hi,
I tried to use the following code to initialize a ROM.

module my_hardware(/*some ports*/);

/* other code that is synthesizable.
............
*/

//synopsys translate_off
file = $fopen("data/mem.data", "r");
for(i = 0; i < ENTRYS;i = i + 1)
begin
$fscanf(file, "%h %h %h %h", temp_th0, temp_th1, temp_th2,
temp_th3);
thetas[3:0] = temp_th0;
thetas[7:4] = temp_th1;
thetas[11:8] = temp_th2;
thetas[15:12] = temp_th3;

$fscanf(file, "%b", temp1);
endbit = temp1;
$fscanf(file, "%d", temp2);
count_bit = temp2;
end
$fclose(file);
//synopsys translate_on

endmodule

But the initialization code aren't synthesizable. This will cause a
simulation-synthesis mismatch.
Does somebody have some ideas?

Peng

 

[goran@xprt.net]

I had the same problem, called the synthesis tool support and was told
it is impossible to do. I ended up filling the ROM after synthesis and
implementation using 'data2bram' (Xilinx). This is done during the bit
file generation. It worked for me because I could change the content
of memory without running the synthesis and implementation.

 

[Peng Yu]

goran@xprt.net (goran@xprt.net) wrote in message news:<cac250d2.0308131423.60e7eb99@posting.google.com>...

I had the same problem, called the synthesis tool support and was told
it is impossible to do. I ended up filling the ROM after synthesis and
implementation using 'data2bram' (Xilinx). This is done during the bit
file generation. It worked for me because I could change the content
of memory without running the synthesis and implementation.
If I use synopsys Behavioral Compiler, what can I do?

 

[Chris Briggs]

We did this here. The answer is to write a program or script that
generates the Verilog code for the ROM using the values in your
mem.data file. The script could either write the whole module or just
the case statement, though I suggest having it write the module.

-cb

 

[Peng Yu]

chris@engim.com (Chris Briggs) wrote in message news:<f8e87dac.0308140627.4014d8a7@posting.google.com>...

We did this here. The answer is to write a program or script that
generates the Verilog code for the ROM using the values in your
mem.data file. The script could either write the whole module or just
the case statement, though I suggest having it write the module.
Could you give me an example?

 

[Chris Briggs]

Example:

File rom.dat is an ASCII file with the ROM contents as 32-bit hex
values (i.e., suitable for $readmemh). E.g.,

020AB510
FB002000
55910030
....

Here's some pseudo-perl for generating the Verilog file, rom.v.
Details of the ROM interface and design are left as an exercise for
the reader. Adjust sizes accordingly. (And please forgive the amateur
perl and any syntax mistakes.)

open ROM_DAT, "rom.dat";
open ROM_V, ">rom.v";

printf ROM_V "module rom(addr, data);\n\n";
printf ROM_V "input [9:0] addr;\n";
printf ROM_V "output [31:0] data;\n\n";
printf ROM_V "reg [31:0] data;\n\n";
printf ROM_V "always @(addr)\n";
printf ROM_V " case (addr)\n";

my $addr;
$addr = 0;

while (<ROM_DAT&gt {
printf ROM_V " 10'd%d: data = 32'h%x;\n", $addr, $_;
$addr++;
}

printf ROM_V " endcase;\n\n";
printf ROM_V "endmodule\n;
close ROM_V;
close ROM_DAT;


Running this script creates rom.v. Instantiate that in your design and
you should be good to go. You might want to add a default case that
either displays an error message or gives a clearly bogus value (e.g.,
32'hFEEDFACE) so you know when the ROM-reading logic went out of
bounds.

-cb