How to instantiate DPRAM in Synplify Pro

[srini]

Hi,
I created a DPRAM using LogiCore in Xilinx and instantiated it in my
top module. When I synthesize it in Synplify Pro 8.4, I am getting a
warning, "creating black box for dpram". Its not taking it as a
BlockRam for synthesis. What should I do so that it get synthesized?
In general I want to know the procedure to instantiate any coregen
compenet like DCM and the like for synthesis in Synplify Pro.

Thanks & Regards,
Srini.

 

[John_H]

srini wrote:

Hi,
I created a DPRAM using LogiCore in Xilinx and instantiated it in my
top module. When I synthesize it in Synplify Pro 8.4, I am getting a
warning, "creating black box for dpram". Its not taking it as a
BlockRam for synthesis. What should I do so that it get synthesized?
In general I want to know the procedure to instantiate any coregen
compenet like DCM and the like for synthesis in Synplify Pro.

Thanks & Regards,
Srini.

The coregen produces a file for the function. If it's RTL, SynplifyPro
needs to have that file added. If the file is a netlist, the netlist
location needs to be specified in the Xilinx back end tool and the RTL
black box produced *by* the Coregen needs to be included in your
Synplicity project. When you tell the tool it's a black box with that
file, there will be no warning that the component instantiated in your
code with no other information is treated as a black box because you
*have* provided other information explicitly making it a black box.

And you can infer the dual port rams yourself rather than using a
Coregen module.

And you can use one of the modules in the unisim.v or unisim.vhd file
that's automatically included in your Xilinx project such as
RAMB16_S9_S18 which provides different input and output port widths. (I
don't think the different widths infer nicely just yet)

 

[gongguowang@yahoo.com]

you can directly add the ".edn" file which generated by coregen to ur
syplify project, and run