How to initialize inferred RAM

[kyrten]

Is it possible to initialize inferred RAM for simulation?
I tried like for BlockRAM but ModelSim don't accept.

I'm using XST 6.1 and Modelsim XE II 5.7c

 

[John_H]

For simulation, I initialize my inferred ram using an initial block.

reg [7:0] Array [255:0];
initial
begin
Array[0] = 8'h13;
Array[1] = 8'hfe;
....
end

I'm hoping to see the support of initial blocks for FPGAs in synthesizers
soon so we can use the initial blocks for BOTH simulation and synthesis.
Ohhhh, wouldn't that be nice!


"kyrten" <kyrten@noreply.com> wrote in message
news:ca8j70dgqg13llql5istkh17h52k77k9ej@4ax.com...

Is it possible to initialize inferred RAM for simulation?
I tried like for BlockRAM but ModelSim don't accept.

I'm using XST 6.1 and Modelsim XE II 5.7c

 

[ka]

On Mon, 12 Apr 2004 19:44:22 GMT, "John_H" <johnhandwork@mail.com>
wrote:

For simulation, I initialize my inferred ram using an initial block.

reg [7:0] Array [255:0];
initial
begin
Array[0] = 8'h13;
Array[1] = 8'hfe;
...
end

I'm hoping to see the support of initial blocks for FPGAs in synthesizers
soon so we can use the initial blocks for BOTH simulation and synthesis.
Ohhhh, wouldn't that be nice!


"kyrten" <kyrten@noreply.com> wrote in message
news:ca8j70dgqg13llql5istkh17h52k77k9ej@4ax.com...
Is it possible to initialize inferred RAM for simulation?
I tried like for BlockRAM but ModelSim don't accept.

I'm using XST 6.1 and Modelsim XE II 5.7c

You can always use a $readmemh or $readmemb if individual assigns
become too bothersome.

 

[Jeremy Webb]

Hi.

Take a look at page 1505 in the Libraries Guide of Xilinx ISE. There
you'll see examples of Verilog instantiations for simulation.

NOTE: For synthesis you'll need to use the "//synthesis" attribute.
See the Constraints Guide of Xilinx ISE for more information on the
synthesis versions of Block RAM initialization.

You'll find the Xilinx ISE manual in the docs folder in the install
directory of the Xilinx ISE program.

Hope this helps,

Jeremy

kal<kal@dspia.deletethis.com> wrote in message news:<9q2m701iardoicvl2vtd6os873e7rorma8@4ax.com>...

On Mon, 12 Apr 2004 19:44:22 GMT, "John_H" <johnhandwork@mail.com
wrote:

For simulation, I initialize my inferred ram using an initial block.

reg [7:0] Array [255:0];
initial
begin
Array[0] = 8'h13;
Array[1] = 8'hfe;
...
end

I'm hoping to see the support of initial blocks for FPGAs in synthesizers
soon so we can use the initial blocks for BOTH simulation and synthesis.
Ohhhh, wouldn't that be nice!


"kyrten" <kyrten@noreply.com> wrote in message
news:ca8j70dgqg13llql5istkh17h52k77k9ej@4ax.com...
Is it possible to initialize inferred RAM for simulation?
I tried like for BlockRAM but ModelSim don't accept.

I'm using XST 6.1 and Modelsim XE II 5.7c


You can always use a $readmemh or $readmemb if individual assigns
become too bothersome.