How to infer internal block RAMs?

[kool]

Dear all!
I am struck with a problem with my Xilinx ISE.I am trying to synthesise
a 10 port register file with 40 bit registers.When I am trying to
synthesise, it takes exponential time and says to try to use the
internal block and distributed RAM resources available on the Spartan
board(Spartan XC3S5000). I also tried to infer RAM as reg[39:0]
RAM[15:0] (by searching Xilinx FAQs) but then it didnt
synthesise(though when i implemented it as a single RAM,not in my reg
file logic it inferred the block RAMs).Can anyone help me out how to
solve it? I have to implement multiport multiple(3) reg banks.

 

Inferring RAM works with FPGA Express, but I've never been able to get
XST to do it. (XST is the default synthesizer for ISE.)

My work-around was to use coregen to generate the RAMs, and instantiate
them rather than inferring them.

Until someone smarter than us comes along, you might try that.

 

[kool]

Hey!
Thanx for the CoreGen part.Well actually if u go to
http://toolbox.xilinx.com/docsan/xilinx7/books/data/docs/xst/xst0027_5.html
u will see XST actually infers the internal RAM but somehow I couldnt
use
it in my design. Actually I had tried the Core part too before,but I
was not
able to build my logic as I didnt know how to pass address to a
Register
file module(which will be generated by COreGen) as I have to pass
address
for read and write from top level module,I presume I have some very
grave
weakness with my Verilog basics..If you can please show me the light..
Thanx again,
Kool

 

You instantiate it just like any other module. Coregen leaves behind a
dot-veo file (ie kool_ram.veo). In it are instructions for
instantiating it.

 

[johnp]

I have inferred block ram many times using XST. Below is some sample
code.
You need to be aware that using block ram requires that the read
operation
be synchronous.

John Providenza

reg [8:0] out_ptr;
reg [7:0] out_buf [511:0];
reg [8:0] out_rd_addr;
always @(posedge clk)
if (fast_wr)
out_buf[out_ptr] <= fast_wr_data;

always @(posedge clk)
out_rd_addr <= out_ptr;

assign out_wr_data = out_buf[out_rd_addr];

 

[Andy Peters]

kool wrote:

Dear all!
I am struck with a problem with my Xilinx ISE.I am trying to synthesise
a 10 port register file with 40 bit registers.When I am trying to
synthesise, it takes exponential time and says to try to use the
internal block and distributed RAM resources available on the Spartan
board(Spartan XC3S5000). I also tried to infer RAM as reg[39:0]
RAM[15:0] (by searching Xilinx FAQs) but then it didnt
synthesise(though when i implemented it as a single RAM,not in my reg
file logic it inferred the block RAMs).Can anyone help me out how to
solve it? I have to implement multiport multiple(3) reg banks.

Did you bother to RTFM? it'll tell you how to write your code so you
can infer RAMs.

-a