How to increase data of std_logic_vector by 1 in VHDL-2002...

[W TX]

Hi,
It is a long time headache for me to increase a data of std_logic_vector by 1.

Here are examples:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;

constant ONE : std_logic_vector(7 downto 0);
signal Series_Number : std_logic_vector(7 downto 0);
....
All followings generate errors in VHDL-2002:
Series_Number <= Series_Number +1;
Series_Number <= Series_Number +\'1\';
Series_Number <= Series_Number+std_logic_vector(unsigned(Series_Number)+1);
Series_Number <= Series_Number+ONE;

Thank you.

Weng