How to include don't care minterms

[Gregory Huffman]

Hi Group:

I need to know how to include don't care minterms in boolean equations
written in VHDL to be synthesized with Synopsys.

For example, I have a combinatorial equation stating the following:

f(ABC) = m(2, 7) + d(3, 6)

The equation entered in VHDL has to include the don't care terms. This
is for a mental gymanistic in Synopsys to see the effect of including
don't care terms.

The m(2, 7) are minterms corresponding to k-map cells 2 and 7, and the
d(3, 6) are don't care minterms corresponding to k-map cells 3 and 6
for a three variable k-map.

Any suggestions are helpfull.

Regards,
G.

 

[Egbert Molenkamp]

"Gregory Huffman" <gthuffman@att.net> schreef in bericht
news:jb0a109aid6hcoonegh20rbkrler1q93ff@4ax.com...

Hi Group:

I need to know how to include don't care minterms in boolean equations
written in VHDL to be synthesized with Synopsys.

For example, I have a combinatorial equation stating the following:

f(ABC) = m(2, 7) + d(3, 6)

The equation entered in VHDL has to include the don't care terms. This
is for a mental gymanistic in Synopsys to see the effect of including
don't care terms.

The m(2, 7) are minterms corresponding to k-map cells 2 and 7, and the
d(3, 6) are don't care minterms corresponding to k-map cells 3 and 6
for a three variable k-map.

Any suggestions are helpfull.

Maybe this is a solution:
- n is the number of inputs; three in your case (C,B,A)
- minterms and maxterm contains the position with the '1' and the don't
care's.

I'm interested in the effects you will find using the don't cares.

Best Regards,

Egbert Molenkamp


library ieee;
use ieee.std_logic_1164.all;
entity kmap is
generic (n : positive := 3); -- number of input
port (i : in std_logic_vector(n-1 downto 0);
t : out std_logic_vector(2**n-1 downto 0); -- for testing purpose
only
o : out std_logic);
end kmap;

library ieee;
use ieee.numeric_std.all;
architecture test of kmap is
type int_vec is array (natural range <&gt of integer;
constant minterms : int_vec := (2,7);
constant dontcares : int_vec := (3,6);
function fill_map (minterm, dontcares : int_vec; n : natural) return
std_logic_vector is
variable res : std_logic_vector(2**n-1 downto 0);
begin
res := (others => '0');
for i in minterms'range loop
assert (minterms(i)>=0) and (minterms(i)<2**n) report "minterm out of
range" severity error;
res(minterm(i)) := '1';
end loop;
for i in dontcares'range loop
assert (dontcares(i)>=0) and (dontcares(i)<2**n) report "dontcare out
of range" severity error;
res(dontcares(i)) := '-';
end loop;
return res;
end fill_map;
constant m : std_logic_vector(2**n-1 downto 0) :=
fill_map(minterms,dontcares,n);
begin
t <= m; -- for testing purpose only
o <= m(to_integer(unsigned(i)));
end test;

 

[Jonathan Bromley]

"Gregory Huffman" <gthuffman@att.net> wrote in message
news:jb0a109aid6hcoonegh20rbkrler1q93ff@4ax.com...

I need to know how to include don't care minterms in boolean equations
written in VHDL to be synthesized with Synopsys.

For example, I have a combinatorial equation stating the following:

f(ABC) = m(2, 7) + d(3, 6)

The equation entered in VHDL has to include the don't care terms. This
is for a mental gymanistic in Synopsys to see the effect of including
don't care terms.

The m(2, 7) are minterms corresponding to k-map cells 2 and 7, and the
d(3, 6) are don't care minterms corresponding to k-map cells 3 and 6
for a three variable k-map.

Why not enumerate all the k-map cells using a case statement?

(assuming A, B, C, Y are std_logic)

process (A, B, C);
subtype SLV3 is std_logic_vector(2 downto 0);
begin
case SLV3'(A & B & C) is
when "010" | "111" => -- Minterms
y <= '1';
when "011" | "110" => -- Don't-care terms
y <= '-';
when "000" | "001" | "100" | "101" =>
y <= '0';
when others => -- only to mop up meta-values
y <= 'X';
end case;
end process;

Assigning 'X' or '-' to an output should encourage any
decent synthesis tool to do some don't-care optimisations.

--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Gregory Huffman]

On Mon, 26 Jan 2004 12:07:50 GMT, Gregory Huffman <gthuffman@att.net>
wrote:

Thanks to all who responded. The solution I went with was an
applicaiton of the Conditional Signal Assignment Statement. The VHDL
was coded as such:

entity logicblock is
port (a, b, c : in std_logic;
f : out std_logic);
end logicblock;

architecture rtl of logicblock is
signal mt : std_logic;
begin
mt <= a & b & c;

f <= '1' when mt = "010" else
'1' when mt = "111" else
'-' when mt = "011" else
'-' when mt = "110" else
'0';
end rtl

Synopsys gobbled up this logic and very nicely produced optimized
logic with shared minterms, thus minimizing the total gate count.

Hi Group:

I need to know how to include don't care minterms in boolean equations
written in VHDL to be synthesized with Synopsys.

For example, I have a combinatorial equation stating the following:

f(ABC) = m(2, 7) + d(3, 6)

The equation entered in VHDL has to include the don't care terms. This
is for a mental gymanistic in Synopsys to see the effect of including
don't care terms.

The m(2, 7) are minterms corresponding to k-map cells 2 and 7, and the
d(3, 6) are don't care minterms corresponding to k-map cells 3 and 6
for a three variable k-map.

Any suggestions are helpfull.

Regards,
G.