S
shube
Guest
Any Idea how to implement the following, saving hardware as much as
possible?
An AHB address bus that reads from a memory source and writes to 2 dst
buffers (limited in depth) in a round robin manner. both read and write
are in increasing 0x4 modification, for example:
()- src addr
[]- dst1 addr
{}- dst2 addr
(0x200);[0x10];(0x204);[0x14];(0x208);[0x18];(0x20c);{0x40};(0x210);{0x44};(0x214);{0x48};(0x218);[0x10];(0x220);[0x14]...
possible?
An AHB address bus that reads from a memory source and writes to 2 dst
buffers (limited in depth) in a round robin manner. both read and write
are in increasing 0x4 modification, for example:
()- src addr
[]- dst1 addr
{}- dst2 addr
(0x200);[0x10];(0x204);[0x14];(0x208);[0x18];(0x20c);{0x40};(0x210);{0x44};(0x214);{0x48};(0x218);[0x10];(0x220);[0x14]...