How to implement Random function

[Karthikeyan Subramaniyam]

Hi all,
I'm trying to port Verilog code to VHDL. In that I've $random system
task in verilog code. Can anyone support me to implement in VHDL
simplest way.

----
reg seq;
always
begin
#10 seq = $random;
end
----

like,

signal seq : std_logic;
.....

Thanks & Regards,
Karthik

 

[Mike Treseler]

Karthikeyan Subramaniyam wrote:

Hi all,
I'm trying to port Verilog code to VHDL. In that I've $random system
task in verilog code. Can anyone support me to implement in VHDL
simplest way.

See the function "randomize" in the process tb_clk
in the testbench here:

http://home.comcast.net/~mike_treseler/test_uart.vhd


-- Mike Treseler

 

[Barry Brown]

Package IEEE.math.real defines a function uniform for random variables.


"Karthikeyan Subramaniyam" <karthiks@toNomOucShsPemAi.coMm> wrote in message
news:dtm45f$3u3$1@home.itg.ti.com...

Hi all,
I'm trying to port Verilog code to VHDL. In that I've $random system
task in verilog code. Can anyone support me to implement in VHDL
simplest way.

----
reg seq;
always
begin
#10 seq = $random;
end
----

like,

signal seq : std_logic;
....

Thanks & Regards,
Karthik