how to implement module for cap measurem

[yvk]

Hi,

I want to understand if this is really implementable.

requirem is to create a circuit/verilogA model which has to 2 terminals where the cap(DUT) is to be connected. And from the results of an AC simulation with Vac/Iac through this 2 terminals esimate the cap value(little bit of math) and annotate it back to the schematic instance.

thanks,
yvk

 

[Andrew Beckett]

On 01/28/13 19:39, yvk wrote:

Hi,

I want to understand if this is really implementable.

requirem is to create a circuit/verilogA model which has to 2
terminals where the cap(DUT) is to be connected. And from the results of

an AC simulation with Vac/Iac through this 2 terminals esimate the cap
value(little bit of math) and annotate it back to the schematic instance.

thanks,
yvk

That sounds tricky to me, since Verilog-A models are described in the
time domain.

Andrew.

 

[yvk]

Hi Andrew,

It need not be VerilogA, can any such module/block be created(may be using addnl skil,ocean coding as well)

so that the testing and processing of the results is self contained it.

Thanks,
yvk


On Wednesday, February 20, 2013 2:54:55 AM UTC+5:30, Andrew Beckett wrote:

On 01/28/13 19:39, yvk wrote:

Hi,



I want to understand if this is really implementable.



requirem is to create a circuit/verilogA model which has to 2

terminals where the cap(DUT) is to be connected. And from the results of

an AC simulation with Vac/Iac through this 2 terminals esimate the cap

value(little bit of math) and annotate it back to the schematic instance.



thanks,

yvk





That sounds tricky to me, since Verilog-A models are described in the

time domain.



Andrew.

 

[Andrew Beckett]

On 02/20/13 19:15, yvk wrote:

Hi Andrew,

It need not be VerilogA, can any such module/block be created(may be using addnl skil,ocean coding as well)

so that the testing and processing of the results is self contained it.

Thanks,
yvk

I'm sure you could do this with a bit of SKILL code. Unfortunately I
don't have the time to write it myself - maybe you could contact
customer support at http://support.cadence.com ?

Andrew.

 

[yvk]

Thanks Andrew,

Its even not my primary requirement, but just wanted to know the implementation procedure so that I can learn it.

-yvk

On Sunday, February 24, 2013 6:48:15 PM UTC+5:30, Andrew Beckett wrote:

On 02/20/13 19:15, yvk wrote:

Hi Andrew,



It need not be VerilogA, can any such module/block be created(may be using addnl skil,ocean coding as well)



so that the testing and processing of the results is self contained it.



Thanks,

yvk





I'm sure you could do this with a bit of SKILL code. Unfortunately I

don't have the time to write it myself - maybe you could contact

customer support at http://support.cadence.com ?



Andrew.