how to implement LUT(look-up table) in Verilog

[thomasc]

Hi all,
I'd like to find out how to implement LUT in Verilog.

I've seen two ways to do so:
1) using CASE statement and 2) assigning the values of LUT in "always
@(posedge clk)" block.
I thought it might also be possible to 3) have a memory in the size of
LUT and assign each values from the beginning, then refer to(or copy)
its values by indexing(or addressing). I'd like to find out the
diffeerences among these three possible ways and know which is the best
way to implement LUT.

Below is examples of the three ways.
Please let me know which method I'd better choose.
thanks in advance!

// 1) case statement
reg [7:0] LUT [0:15];
always @ (addr) begin
case (addr)
0: out = 8'h0F;
1: out = 8'h00;
2: out = 8'h01;
.
.
.
endcase

// 2) assigning in "always @(posedge clk)" block
always@(posedge clk) begin
LUT[0] = 8'h0F;
LUT[1] = 8'h00;
LUT[2] = 8'h01;
.
.
.

// 3) having memory for LUT and referring by idexing
reg [7:0] LUT [0:15] = {8'h0F,8'h00,8'h01,...};

 

[Neo]

I feel the first and the third options are the likely ones and as such
dont differ much, but the case method looks clearer. I dont like the
the 2nd one with the clock as it will not exactly map to LUT and
moreover the simulation perromance suffers. I would like to know what
others feel.

 

[Berty]

Regardless of the syntax to decide how to write what ever you want to
do you need first to decide what you want it to be and where do you
want it to be located.

Adding a posedge of clk mean that there will be a FF so the decision as
for the use of posedge is determine by do you want there a FF or not.

As for memory, it is an excellent way to build big LU without
"wasting" the FPGA logic assuming of course that you a spare memory
to use.

If you indeed want the LUT to be in a memory you should open the memory
wizard and define the value and generate a pre-program memory which can
be "rom" like or "ram" like base. if you already have the
memory and don't want to go through the wizard you can always open
the edif (edn) file and modify the value which are usually 0 by default
however this you need to be caredfull as sometime the value are not
sequential as for example 24 bit width can be built from 16 and 8 so if
you never "play" with edif file you might want to simple use the
wizard.

So before you decide how to write you need to decide what you want to
do.

Have fun