How to implement gated clock and/or gated partial circuit in

[walala]

Dear all,

I heard about a quite effective low power technique buzzword: "gated clock"
and/or "gated" sub-circuit for long. But I don't know how to implement this
in Verilog? Can anybody point me to some resources which have
easy-to-understand and practical samples or template that I can follow...?

Thanks a lot,

-Walala

 

[Sajan]

Clock gating is done while synthesis and not while doing the RTL using verilog,
Please correct me if i am wrong.
While doing synthesis you can switch clock gating on or off.
Design compiler provides an option for that.

Regards,
Sajan.

"walala" <mizhael@yahoo.com> wrote in message news:<bkhrcc$fhv$1@mozo.cc.purdue.edu>...

Dear all,

I heard about a quite effective low power technique buzzword: "gated clock"
and/or "gated" sub-circuit for long. But I don't know how to implement this
in Verilog? Can anybody point me to some resources which have
easy-to-understand and practical samples or template that I can follow...?

Thanks a lot,

-Walala

 

[Prasanth Kumar]

In Xilinx you can do something like:

module (q, d, clk, rst, ce);
ouput q;
input d, clk, rst, ce;
reg q;

always@ (posedge clk or posedge rst)
begin
if (rst) q <= 0;
else if (ce) q <= d;
end

endmodule

A good reference is the Xilinx documentation xst.pdf and lib.pdf.
I would provide you a link but I can't connect to there right now.

"walala" <mizhael@yahoo.com> wrote in message
news:bkhrcc$fhv$1@mozo.cc.purdue.edu...

Dear all,

I heard about a quite effective low power technique buzzword: "gated
clock"
and/or "gated" sub-circuit for long. But I don't know how to implement
this
in Verilog? Can anybody point me to some resources which have
easy-to-understand and practical samples or template that I can follow...?

Thanks a lot,

-Walala

 

[John_H]

Actually, using a clock enable on the register and leaving the clock tree
active doesn't reduce power like the gated clock that the original poster
asked about.

While Xilinx has BUFGMUX primitives for switching between clocks, I'm left
wondering if the special glitch-protection mechanism won't work properly
when the other side of the MUX is a static logic level. If you use the
Xilinx device, please look at the libraries guide for the details on that
primitive.

For other FPGAs or ASICs, there are possibly library elements that produce a
clean, low propagation gated clock.

With smaller device geometries increasing transistor leakage for our target
speeds, the idle power may be a significantly larger part of device
dissipation than a properly gated clock.

Bottom line, you want a clock net that's fed by an element that will pass
the clock or leave the clock level static in order to reduce the power
dissipated by charging and discharging the clock tree. If you leave your
verilog code with a clock signal that has the gate embedded in it without
taking precautions to force the implementation as a net rather than the
logical equivalent, your results may be less than what you expect.

"Prasanth Kumar" <lunix@comcast.net> wrote in message
news:w2Qbb.552019$o%2.243799@sccrnsc02...

In Xilinx you can do something like:

module (q, d, clk, rst, ce);
ouput q;
input d, clk, rst, ce;
reg q;

always@ (posedge clk or posedge rst)
begin
if (rst) q <= 0;
else if (ce) q <= d;
end

endmodule

A good reference is the Xilinx documentation xst.pdf and lib.pdf.
I would provide you a link but I can't connect to there right now.

"walala" <mizhael@yahoo.com> wrote in message
news:bkhrcc$fhv$1@mozo.cc.purdue.edu...
Dear all,

I heard about a quite effective low power technique buzzword: "gated
clock"
and/or "gated" sub-circuit for long. But I don't know how to implement
this
in Verilog? Can anybody point me to some resources which have
easy-to-understand and practical samples or template that I can
follow...?

Thanks a lot,

-Walala

 

[Ian Poole]

Check out this link:
http://parmita.com/chipguru/issue1/clock_switch.htm
The verilog (or VHDL) should be easy to derive from his schematics.

--
Ian Poole, Consultant

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.


"walala" <mizhael@yahoo.com> wrote in message
news:bkhrcc$fhv$1@mozo.cc.purdue.edu...

Dear all,

I heard about a quite effective low power technique buzzword: "gated
clock"
and/or "gated" sub-circuit for long. But I don't know how to implement
this
in Verilog? Can anybody point me to some resources which have
easy-to-understand and practical samples or template that I can follow...?

Thanks a lot,

-Walala