How to implement a 32 bit multiplier?

[Giox]

Hello everybody, I'm interested in the implementation of a 32x32 bit
multiplier (unsigned values). The target FPGA is Virtex V300e
I would like to implement a system that is not too big, while I have
not a lot of timing constraints. Using a behavioral approach I obtain a
multiplier that needs about 17% of the FPGA, I would like to reduce
this size and the target frequency is about 70Mhz.
Where can I find some good manual that can help me in this task? can
you give me some advice about how to code this device?
Any help will be appreciated.

 

[raul]

If this is application-specific you might be better off doing shifts
and adds.

a << 1 is a*2
a << 2 is a*4
(a<<1)+a is a*3

and so on.