How to handle different proccessing speeds?

[Guenter Dannoritzer]

Hello,

I am a newbie in VHDL and have not much experience with FPGA
implementation. To change that I am doing a self-study project that
includes implementing some signal processing functions in VHDL and
putting it on a Spartan II.

To start simple I am working on a cyclic prefix function. Input to the
function are 512 samples from an IFFT and the function adds 32 samples
to the 512 samples. So my problem is now that I have 512 samples coming
in and 512+32 samples going out. The output is supposed to go to a DAC,
so that sampling rate will be constant. What makes this a bit more
complicated is that the prefix adding can be disabled. So if enabled it
outputs 512+32 samples and disabled only the 512 samples.

I was thinking about two different ways of doing that. One is to adjust
the processing rate of the IFFT and the input frequency of the cyclic
prefix block and keep the output frequency constant for the DAC. This
would lead to a quite crooked frequencies for the IFFT and I have no
experience whether that is actually feasible.

The other idea is to have the IFFT deliver the 512 samples and then stop
its processing for 32 samples.

Is my first thought about the different clock frequencies actually feasible?

Can anybody give me some thoughts about what is a common way of handling
different processing speeds with FPGA implementations?

The second thought seems more intuitive? Is that the way of doing things
or is there a better way?

Thanks for the help.

Guenter

p.s.: I am waiting on a FPGA book in the mail that hopefully helps me
beef up my knowledge in that field. For the time being I was just eager
to go on with my design and hear some expert opinions.

 

[john]

Hi,
I am a kind of newbie too. But this much I know. IF ever u need to
interface two different clock domains u use an asnchronous FIFO. Now
consider a deep enough FIFO for ur application. Let whatever be written in,
it can be read out at different clock rate. Again I'm a newbie and there can
be better suggestions.
--
Joji John ( nansung444@yahoo.com)
"Cogito; ergo sum"
" plain text reduces headaches"
http://www.angelfire.com/ma3/joji
http://geocities.com/nansung444
"Guenter Dannoritzer" <dannoritzer@web.de> wrote in message
news:c8kihm$i15$07$1@news.t-online.com...

Hello,

I am a newbie in VHDL and have not much experience with FPGA
implementation. To change that I am doing a self-study project that
includes implementing some signal processing functions in VHDL and
putting it on a Spartan II.

To start simple I am working on a cyclic prefix function. Input to the
function are 512 samples from an IFFT and the function adds 32 samples
to the 512 samples. So my problem is now that I have 512 samples coming
in and 512+32 samples going out. The output is supposed to go to a DAC,
so that sampling rate will be constant. What makes this a bit more
complicated is that the prefix adding can be disabled. So if enabled it
outputs 512+32 samples and disabled only the 512 samples.

I was thinking about two different ways of doing that. One is to adjust
the processing rate of the IFFT and the input frequency of the cyclic
prefix block and keep the output frequency constant for the DAC. This
would lead to a quite crooked frequencies for the IFFT and I have no
experience whether that is actually feasible.

The other idea is to have the IFFT deliver the 512 samples and then stop
its processing for 32 samples.

Is my first thought about the different clock frequencies actually
feasible?

Can anybody give me some thoughts about what is a common way of handling
different processing speeds with FPGA implementations?

The second thought seems more intuitive? Is that the way of doing things
or is there a better way?

Thanks for the help.

Guenter

p.s.: I am waiting on a FPGA book in the mail that hopefully helps me
beef up my knowledge in that field. For the time being I was just eager
to go on with my design and hear some expert opinions.

 

[Guenter Dannoritzer]

Hi John,


john wrote:

Hi,
I am a kind of newbie too. But this much I know. IF ever u need to
interface two different clock domains u use an asnchronous FIFO. Now
consider a deep enough FIFO for ur application. Let whatever be written in,
it can be read out at different clock rate. Again I'm a newbie and there can
be better suggestions.
--
Joji John ( nansung444@yahoo.com)

[snip]

Thanks for that pointer, I found some code and will study it.

Guenter