How to go to ASIC?...

[Philipp Klaus Krause]

Hello.

I want to do a small design (about 1 mm² die, about 8 pins) with on-chip
oscillator, small SRAM, Flash (or other OTP memory) and maybe an ADC.
I\'d go for an older process such as 0.18 µm; the ASIC shouldn\'t be too
fussy about supply voltage and should work in a range of 2.3 V to 5.5 V.
I\'m looking for low (approx 0.01 €) per-device cost.

I do have some experience using Verilog RTL for CPLDs and FPGAs, but
have never designed an ASIC. So now I wonder how much effort it would be
to take an FPGA-proven design to an ASIC.

What resources (books, websites) should I look into?

What options do I have in terms of doing most of the work myself vs.
contracting out parts of it?
Obviously, I want to do the Verilog RTL design myself, and I don\'t want
to operate my own fab, but I guess there are a lot of options in between.

I tend to prefer using FOSS tools where possible.

Philipp

 

[Johann Klammer]

On 11/03/2020 04:26 PM, Philipp Klaus Krause wrote:

Hello.

I want to do a small design (about 1 mm² die, about 8 pins) with on-chip
oscillator, small SRAM, Flash (or other OTP memory) and maybe an ADC.
I\'d go for an older process such as 0.18 µm; the ASIC shouldn\'t be too
fussy about supply voltage and should work in a range of 2.3 V to 5.5 V.
I\'m looking for low (approx 0.01 €) per-device cost.

I do have some experience using Verilog RTL for CPLDs and FPGAs, but
have never designed an ASIC. So now I wonder how much effort it would be
to take an FPGA-proven design to an ASIC.

What resources (books, websites) should I look into?

What options do I have in terms of doing most of the work myself vs.
contracting out parts of it?
Obviously, I want to do the Verilog RTL design myself, and I don\'t want
to operate my own fab, but I guess there are a lot of options in between.

I tend to prefer using FOSS tools where possible.

Philipp

I believe there were conversion offer for those old ATMEL parts (the AT40k)
not sure if that still exists. Maybe on the microchip website...
You go look yourself, coz it doesn\'t work on my box anymore.

Google has put up a bunch of design rules on github
<https://github.com/google/skywater-pdk>

magic is the classical FOSS VLSI layout tool, but I
don\'t know if you really want to do things down at the
transistor level.
<http://opencircuitdesign.com/magic/>

Parallax (propeller) seems to be fabless and they put
some of their docs online. maybe look there how they do stuff.
<https://docs.google.com/document/d/1gn6oaT5Ib7CytvlZHacmrSbVBJsD9t_-kmvjd7nUR6o/edit?usp=sharing>
<https://github.com/parallaxinc/propeller>

 

[HT-Lab]

On 03/11/2020 15:26, Philipp Klaus Krause wrote:

Hello.

I want to do a small design (about 1 mm² die, about 8 pins) with on-chip
oscillator, small SRAM, Flash (or other OTP memory) and maybe an ADC.
I\'d go for an older process such as 0.18 µm; the ASIC shouldn\'t be too
fussy about supply voltage and should work in a range of 2.3 V to 5.5 V.
I\'m looking for low (approx 0.01 €) per-device cost.

I do have some experience using Verilog RTL for CPLDs and FPGAs, but
have never designed an ASIC. So now I wonder how much effort it would be
to take an FPGA-proven design to an ASIC.

What resources (books, websites) should I look into?

What options do I have in terms of doing most of the work myself vs.
contracting out parts of it?
Obviously, I want to do the Verilog RTL design myself, and I don\'t want
to operate my own fab, but I guess there are a lot of options in between.

I tend to prefer using FOSS tools where possible.

Philipp

I would advice to go the MPW route first before going the full
commercial ASIC route (assuming you have the budget):

https://europractice-ic.com/

Even with MPW you are still looking at serious money (>5K euros). I also
suspect you will struggle to get FLASH/ADC on the same low cost technology.

In terms of effort required, well I would just say wait until you get a
cost estimate..;-) There are many single engineers who design ASIC\'s,
Europractise can help you out (I also believe TU Berlin has done some
designs).

Good luck,
Hans
www.ht-lab.com

 

[Kevin Neilson]

On Tuesday, November 3, 2020 at 8:26:19 AM UTC-7, Philipp Klaus Krause wrote:

Hello.

I want to do a small design (about 1 mm² die, about 8 pins) with on-chip
oscillator, small SRAM, Flash (or other OTP memory) and maybe an ADC.
I\'d go for an older process such as 0.18 µm; the ASIC shouldn\'t be too
fussy about supply voltage and should work in a range of 2.3 V to 5.5 V.
I\'m looking for low (approx 0.01 €) per-device cost.

I do have some experience using Verilog RTL for CPLDs and FPGAs, but
have never designed an ASIC. So now I wonder how much effort it would be
to take an FPGA-proven design to an ASIC.

What resources (books, websites) should I look into?

What options do I have in terms of doing most of the work myself vs.
contracting out parts of it?
Obviously, I want to do the Verilog RTL design myself, and I don\'t want
to operate my own fab, but I guess there are a lot of options in between.

I tend to prefer using FOSS tools where possible.

Philipp

I\'m curious as to why you\'d want to make an ASIC since the effort and cost is huge.

I\'m working on a 7nm ASIC now, but I do the RTL and don\'t know much about the ASIC synthesis or anything about the costs. I found this article from last year estimating mask costs:
https://www.electronicdesign.com/technologies/embedded-revolution/article/21808278/the-economics-of-asics-at-what-point-does-a-custom-soc-become-viable

They report that a mask cost ranges from $1.5m for 28nm to \"sub $100k\" for 180nm. (I wonder what the costs are for my 7nm ASIC are!). I don\'t know if these costs depend on the gate count; I\'d assume so.

You have to make a lot of them to get the per-device cost to 1 Euro-cent. Plus, since it would be 180nm, you might use even more power compared to getting new discrete memory chips and using a new CPLD/FPGA for the custom parts.

But it would be pretty cool if you did make an ASIC.

 

[stevem1]

Right 180nm us a good choice for what you want to do.
Europractice also offers a miniasic version for most of their shuttles. The miniasic
allows smaller block sizes than the regular MPW shuttle. For TSMC180nm-MS/RF the
miniasic blk size is 1.66mm x 1.66mm ~2.755mm^2 and the cost for ~40 bare dies
is 3100euro. Which is ~$3,750 US dollars. So that comes out to about $1,360 for
40 bare dies. And you can order 40 extra dies for a another $1-2K. The regular
TSMC180-MS/RF shuttle is 5mm x 5mm and that would run about

The TSMC180 MS/RF PDK comes with std-cell and IO libraries, so is suitable for the
mixed signal design you mentioned. See the Europractice 2020 prices and schedule at:
https://europractice-ic.com/schedules-prices/

They have also posted their 2021 schedule, but not the prices at:
https://europractice-ic.com/schedules-prices/schedules-2021-2

Muse semiconductor and MOSIS also have TSMC180-MS/RF shuttles and miniasics..

Respond if you need more information, I have run shuttles and miniascis with all three
of these aggregators.

-steve


On Thursday, November 5, 2020 at 8:53:44 PM UTC-6, Kevin Neilson wrote:

On Tuesday, November 3, 2020 at 8:26:19 AM UTC-7, Philipp Klaus Krause wrote:
Hello.

I want to do a small design (about 1 mm² die, about 8 pins) with on-chip
oscillator, small SRAM, Flash (or other OTP memory) and maybe an ADC.
I\'d go for an older process such as 0.18 µm; the ASIC shouldn\'t be too
fussy about supply voltage and should work in a range of 2.3 V to 5.5 V..
I\'m looking for low (approx 0.01 €) per-device cost.

I do have some experience using Verilog RTL for CPLDs and FPGAs, but
have never designed an ASIC. So now I wonder how much effort it would be
to take an FPGA-proven design to an ASIC.

What resources (books, websites) should I look into?

What options do I have in terms of doing most of the work myself vs.
contracting out parts of it?
Obviously, I want to do the Verilog RTL design myself, and I don\'t want
to operate my own fab, but I guess there are a lot of options in between.

I tend to prefer using FOSS tools where possible.

Philipp
I\'m curious as to why you\'d want to make an ASIC since the effort and cost is huge.

I\'m working on a 7nm ASIC now, but I do the RTL and don\'t know much about the ASIC synthesis or anything about the costs. I found this article from last year estimating mask costs:
https://www.electronicdesign.com/technologies/embedded-revolution/article/21808278/the-economics-of-asics-at-what-point-does-a-custom-soc-become-viable

They report that a mask cost ranges from $1.5m for 28nm to \"sub $100k\" for 180nm. (I wonder what the costs are for my 7nm ASIC are!). I don\'t know if these costs depend on the gate count; I\'d assume so.

You have to make a lot of them to get the per-device cost to 1 Euro-cent. Plus, since it would be 180nm, you might use even more power compared to getting new discrete memory chips and using a new CPLD/FPGA for the custom parts.

But it would be pretty cool if you did make an ASIC.