How to gnerate VCD file with hex outputs.

[vssumesh]

Hi all,
I am trying to generate a vcd file from the model sim V6.0a. tried
the following command
vcd file test1.vcd
vcd add -ports /top_module/DUT/*

It is giving all the signals but bus signals are split into separate
bits. How can i genrate a vcd file in which bus signals are combined
(values in hex) rather than bits.

Also in the documentation of model sim i only found the way to gnerate
the vcd file from console. Is there any way to generate that from GUI.
Thanks in advance

 

[Jason Zheng]

Well, you can try putting these in your verilog source file:

$dumpfile ("out.vcd");
$dumpvars (whatever_you_want_to_dump);

These are standard verilog tasks that you can use in any simulator.

vssumesh wrote:

Hi all,
I am trying to generate a vcd file from the model sim V6.0a. tried
the following command
vcd file test1.vcd
vcd add -ports /top_module/DUT/*

It is giving all the signals but bus signals are split into separate
bits. How can i genrate a vcd file in which bus signals are combined
(values in hex) rather than bits.

Also in the documentation of model sim i only found the way to gnerate
the vcd file from console. Is there any way to generate that from GUI.
Thanks in advance

 

[Art Stamness]

IEEE-1364-2001 Sect. 8.2.1 Syntax of four state VCD File :

... Value changes for all other variables [ other than real ,
integer etc. ] are specified
in binary format by 0,1,x, or z values. Strength information and
memories are not
dumped.


The reason they need to do this is simple, if it were represented in
hex / oct any non single bit to single byte translation these value
would be wrong :

bin : 10x0 <== Good
oct : 1X <== Not very helpful
hex : X <== Not helpful at all

-Art

 

[vssumesh]

I wrote a program to convert the vcd to hex format thanks for the
advice.....