ine.GSO.4.58-035.0404070358320.7554@unix3.andrew.cmu.edu...look in the XST templates.Usually your best chance of getting it is with a CASE statement. No
guarantees though as synthesisers are notoriously unpredictable.
You can also try structuring your VHDL to suggest a element layout.
Instantiating macros in your HDL will give you a more exact structure.
--
John Adair
Enterpoint Ltd.
http://www.enterpoint.co.uk
This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.
"Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message
news
I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of using
several 2:1 muxs'.
Is there a suggested coding style to get xst to infer the larger muxes or
how would i hardcode them to make larger muxes?
Thanks
Matt
ine.GSO.4.58-035.0404070358320.7554@unix3.andrew.cmu.edu...ine.GSO.4.58-035.0404070358320.7554@unix3.andrew.cmu.edu...I don't understand how you would make a 4:1 mux in a Xilinx without making
--"Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message
news
I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of using
several 2:1 muxs'.
Is there a suggested coding style to get xst to infer the larger muxes or
how would i hardcode them to make larger muxes?
Thanks
Matt
I don't understand how you would make a 4:1 mux in a Xilinx without making
it out of smaller muxes. The LUTs only have 4 inputs, so you can't make a
4:1 mux out of a single LUT. You need two LUTs plus another F5 mux.
-Kevin
"John Adair" <newsreply@loseinspace.co.uk> wrote in message news:<XVOcc.2$bb6.0@newsr2.u-net.net>...
Usually your best chance of getting it is with a CASE statement. No
guarantees though as synthesisers are notoriously unpredictable.
You can also try structuring your VHDL to suggest a element layout.
Instantiating macros in your HDL will give you a more exact structure.
--
John Adair
Enterpoint Ltd.
http://www.enterpoint.co.uk
This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.
"Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message
news
I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of using
several 2:1 muxs'.
Is there a suggested coding style to get xst to infer the larger muxes or
how would i hardcode them to make larger muxes?
Thanks
Matt
look in the XST templates.
In Verilog
x <=
(sel==0)? a0 :
(sel==1)? a1 :
(sel==2)? a2 :
(sel==3)? a3 :
an
and so on works for me. I've gone to 8 no problem. But occasional use
of hardcoding a MUXxyz can help to build the top stage if you need to
combine say a 2->1 with an earlier 4->1 and so on. There are quite a
few app nots in the xapp dir.
john jakson wrote:
"John Adair" <newsreply@loseinspace.co.uk> wrote in message news:<XVOcc.2$bb6.0@newsr2.u-net.net>...
Usually your best chance of getting it is with a CASE statement. No
guarantees though as synthesisers are notoriously unpredictable.
You can also try structuring your VHDL to suggest a element layout.
Instantiating macros in your HDL will give you a more exact structure.
--
John Adair
Enterpoint Ltd.
http://www.enterpoint.co.uk
This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.
"Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message
news
I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of using
several 2:1 muxs'.
Is there a suggested coding style to get xst to infer the larger muxes or
how would i hardcode them to make larger muxes?
Thanks
Matt
look in the XST templates.
In Verilog
x <=
(sel==0)? a0 :
(sel==1)? a1 :
(sel==2)? a2 :
(sel==3)? a3 :
an
and so on works for me. I've gone to 8 no problem. But occasional use
of hardcoding a MUXxyz can help to build the top stage if you need to
combine say a 2->1 with an earlier 4->1 and so on. There are quite a
few app nots in the xapp dir.
I have not tried coding this in XST, but I am pretty sure it does not
result in an 8:1 mux. The syntax you show is a priority selector. That
means that it indicates an order of precedence. Even though it makes no
difference since the selectors in each case are mutually exclusive, it
is unlikely that this will be optimized to a proper mux.
The recommended coding style would be a case statement, which by
definition has mutually exclusive selections of a single control
variable.
A better coding method for bus muxes would be to pre-decode the
selectors so that each of the 8 mux inputs has a separate enable. Then
an 8 input mux can be done in just two levels of LUTs. The first level
can encode the AND gates and one OR gate for combining two inputs. The
second level is an four input OR gate for the final output.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
--When trying to create a mux with a case statement XST requires the output
be a reg. Why is this and would making it a reg(latch) make the mux
slower?
Matt
On Thu, 8 Apr 2004, rickman wrote:
john jakson wrote:
"John Adair" <newsreply@loseinspace.co.uk> wrote in message news:<XVOcc.2$bb6.0@newsr2.u-net.net>...
Usually your best chance of getting it is with a CASE statement. No
guarantees though as synthesisers are notoriously unpredictable.
You can also try structuring your VHDL to suggest a element layout.
Instantiating macros in your HDL will give you a more exact structure.
--
John Adair
Enterpoint Ltd.
http://www.enterpoint.co.uk
This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.
"Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message
news
I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of using
several 2:1 muxs'.
Is there a suggested coding style to get xst to infer the larger muxes or
how would i hardcode them to make larger muxes?
Thanks
Matt
look in the XST templates.
In Verilog
x <=
(sel==0)? a0 :
(sel==1)? a1 :
(sel==2)? a2 :
(sel==3)? a3 :
an
and so on works for me. I've gone to 8 no problem. But occasional use
of hardcoding a MUXxyz can help to build the top stage if you need to
combine say a 2->1 with an earlier 4->1 and so on. There are quite a
few app nots in the xapp dir.
I have not tried coding this in XST, but I am pretty sure it does not
result in an 8:1 mux. The syntax you show is a priority selector. That
means that it indicates an order of precedence. Even though it makes no
difference since the selectors in each case are mutually exclusive, it
is unlikely that this will be optimized to a proper mux.
The recommended coding style would be a case statement, which by
definition has mutually exclusive selections of a single control
variable.
A better coding method for bus muxes would be to pre-decode the
selectors so that each of the 8 mux inputs has a separate enable. Then
an 8 input mux can be done in just two levels of LUTs. The first level
can encode the AND gates and one OR gate for combining two inputs. The
second level is an four input OR gate for the final output.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
--
ine.GSO.4.58-035.0404080202540.6639@unix3.andrew.cmu.edu...When trying to create a mux with a case statement VERILOG requires the use
Declaring something "reg" does *not* necessarily mean that it will be
Matt
On Thu, 8 Apr 2004, rickman wrote:
john jakson wrote:
"John Adair" <newsreply@loseinspace.co.uk> wrote in message news:<XVOcc.2$bb6.0@newsr2.u-net.net>...
Usually your best chance of getting it is with a CASE statement. No
guarantees though as synthesisers are notoriously unpredictable.
You can also try structuring your VHDL to suggest a element layout.
Instantiating macros in your HDL will give you a more exact structure.
--
John Adair
Enterpoint Ltd.
http://www.enterpoint.co.uk
This message is the personal opinion of the sender and not that necessarily
that of Enterpoint Ltd.. Readers should make their own evaluation of the
facts. No responsibility for error or inaccuracy is accepted.
"Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message
news
I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of using
several 2:1 muxs'.
Is there a suggested coding style to get xst to infer the larger muxes or
how would i hardcode them to make larger muxes?
Thanks
Matt
look in the XST templates.
In Verilog
x <=
(sel==0)? a0 :
(sel==1)? a1 :
(sel==2)? a2 :
(sel==3)? a3 :
an
and so on works for me. I've gone to 8 no problem. But occasional use
of hardcoding a MUXxyz can help to build the top stage if you need to
combine say a 2->1 with an earlier 4->1 and so on. There are quite a
few app nots in the xapp dir.
I have not tried coding this in XST, but I am pretty sure it does not
result in an 8:1 mux. The syntax you show is a priority selector. That
means that it indicates an order of precedence. Even though it makes no
difference since the selectors in each case are mutually exclusive, it
is unlikely that this will be optimized to a proper mux.
The recommended coding style would be a case statement, which by
definition has mutually exclusive selections of a single control
variable.
A better coding method for bus muxes would be to pre-decode the
selectors so that each of the 8 mux inputs has a separate enable. Then
an 8 input mux can be done in just two levels of LUTs. The first level
can encode the AND gates and one OR gate for combining two inputs. The
second level is an four input OR gate for the final output.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Well, there are a few ways I can think of:
1) Use TBUFs to wire-OR LUT outputs together
2) Use the OR cascade in virtexII in the same way, preferable because it
is
faster and more plentiful
3) If you can accept a 16 clock set-up time, you can use the SRL16 as a
programmable LUT. The programmer uses 2.5 slices, and loads up the SRL16
(or a
word wide bank of them) with the appropriate pattern to connect the
selected
input to the output ( patterns are for a mux with enable are
X"0000",X"AAAA",X"CCCC",X"F0F0",X"FF00"). This is useful for minimum
propagation time 4:1 muxes for applications where the selection is
relatively
static, or is otherwise allowed time to complete. Yes, I have used it.
4) if your sources to the mux have available terms or come from
flip-flops, you
can substitute a 4 input OR for each MUX bit by having your select logic
gate
off all but one of the inputs at any given time. If the inputs are from
flip-flops, you can use the sync reset on the flip-flops for the gate
function
without having to add logic in front of the flip-flop other than the
decoder on
the reset.
Kevin Neilson wrote:
"Matthew E Rosenthal" <mer2@andrew.cmu.edu> wrote in message
news
I am trying to get XST to infer an 8:1 or even a 4:1 mux, instead of
using
several 2:1 muxs'.
Is there a suggested coding style to get xst to infer the larger muxes
or
how would i hardcode them to make larger muxes?
Thanks
Matt
I don't understand how you would make a 4:1 mux in a Xilinx without
making
it out of smaller muxes. The LUTs only have 4 inputs, so you can't make
a
4:1 mux out of a single LUT. You need two LUTs plus another F5 mux.
-Kevin
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
--Ray Andraka, P.E.
snipping
I did miss 1 detail, I use the form in both cont = assignments and the