how to get singals on low level VHDL modules

[gongguowang@yahoo.com]

Hi, guys
my Testbench is witten by Verilog, and Top module is VHDL Entity.
I want get signals in Top mmodule in Testbench, It doesn,t work when I
use "testbench.top.signal"$B!)(B Can anyone tell me how to get signals in
VHDL module?

 

[Ryan]

On Dec 11, 10:29 pm, "gongguow...@yahoo.com" <gongguow...@yahoo.com>
wrote:

Hi, guys
my Testbench is witten by Verilog, and Top module is VHDL Entity.
I want get signals in Top mmodule in Testbench, It doesn,t work when I
use "testbench.top.signal"$B!)(B Can anyone tell me how to get signals in
VHDL module?

You are attempting a cross module reference (XMR) from verilog to
VHDL. This goes beyond the Verilog specification, so the behavior/
solution is vendor proprietary. VCS for example does not support
using a verilog XMR into VHDL, you must use the $hdl_xmr system task
instead. Other tools have comparable features.