R
reni
Guest
Hi,
I'm learning synthesis using DC compiler.I have done all the basic steps
of
analyzing,elaborating,setting the wire-load model,constraints and all
that.
.After all this when I take a timing report there are slack violations.How
should i analyze them and get rid of them.
Can anyone tell me the procedure of doing this or suggest any material
which will be helpful.
Kindly help me out.
Regards,
Reni.
I'm learning synthesis using DC compiler.I have done all the basic steps
of
analyzing,elaborating,setting the wire-load model,constraints and all
that.
.After all this when I take a timing report there are slack violations.How
should i analyze them and get rid of them.
Can anyone tell me the procedure of doing this or suggest any material
which will be helpful.
Kindly help me out.
Regards,
Reni.