How to get rid of violations(slack) during synthesis?

R

reni

Guest
Hi,
I'm learning synthesis using DC compiler.I have done all the basic steps
of
analyzing,elaborating,setting the wire-load model,constraints and all
that.
.After all this when I take a timing report there are slack violations.How
should i analyze them and get rid of them.
Can anyone tell me the procedure of doing this or suggest any material
which will be helpful.
Kindly help me out.

Regards,
Reni.
 
Hi Reni,

your worst path is shown in the timing report. Are you shure that you
define
all false path's resp. between different clock domains. Check if your
wireload
mode is correct, i prefer enclosed as wire load mode. If there are
small violations
try compile -map_effort high with your current netlist as base. If
you take a look
in the documentation which will be provided by synopsys you can found a
lot of
hints and proposals for doing a good synthesis job. ( type unix:> sold
& ) to start
documentation

have fun
calzi

reni schrieb:

Hi,
I'm learning synthesis using DC compiler.I have done all the basic steps
of
analyzing,elaborating,setting the wire-load model,constraints and all
that.
.After all this when I take a timing report there are slack violations.How
should i analyze them and get rid of them.
Can anyone tell me the procedure of doing this or suggest any material
which will be helpful.
Kindly help me out.

Regards,
Reni.
 

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