How to get first bit '0' position in certain register?

[Newhand]

Dear all,

For certain register, say stream = 16'b1111010011111111;
the position of first bit '0' is: 8 (from LSB);
if stream = 16'b1111000100010011, then the position is 2;

what I need is to get the position.

Since it should be done in one clock cycle, combination logic in
Verilog might be a better choice.

Could anybody give me some pieces of suggestion? Thanks in advance.

Newhand

 

[Robert Sefton]

This function is called "find first one" and is fairly common. You could
use a for loop or if-else construct in Verilog. Try Googling on "find
first one" - you may find something you can use.

Robert

"Newhand" <newhand@edacn.net> wrote in message
news:e59512cb.0312250715.106d9d97@posting.google.com...

Dear all,

For certain register, say stream = 16'b1111010011111111;
the position of first bit '0' is: 8 (from LSB);
if stream = 16'b1111000100010011, then the position is 2;

what I need is to get the position.

Since it should be done in one clock cycle, combination logic in
Verilog might be a better choice.

Could anybody give me some pieces of suggestion? Thanks in advance.

Newhand

 

[Hal Murray]

This function is called "find first one" and is fairly common. You could
use a for loop or if-else construct in Verilog. Try Googling on "find
first one" - you may find something you can use.

Another term to search on is priority encoder.

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[Peter Alfke]

hmurray@suespammers.org (Hal Murray) wrote in message news:<vumcs7q5nrua43@corp.supernews.com>...

This function is called "find first one" and is fairly common. You could
use a for loop or if-else construct in Verilog. Try Googling on "find
first one" - you may find something you can use.

Another term to search on is priority encoder.
If you can restrict your search to the first 24 bits, and if you have

a Virtex-II BlockRAM available, you can feed the upper 12 bits as
address to one port, and the lower 12 bits as address to the other
port, and make the BlockRAM give you the 4-bit position information
within the 12 address bits. You then have to combine the two port
outputs. You can get the answer in one clock cycle (faster than all
the suggested software solutions) at well over 100 MHz,
ocnservatively.

Peter Alfke, Xilinx Applications (answering from home)
Merry Christmas to everybody on this newsgroup, and an interesting and
interactive 2004!