How to get a list of nets tied to VCC or GND for a netlist?

[Shantanu]

Hi,

I have a netlist in which i have find out which nets are tied to VCC
or GND.
The list should contain hierarchial path of the net and status whether
tied to VCC or GND?

Please let me know how can i do that whether it requires any tool or
script.

Cheers!
Shaan

 

[pallav]

On Aug 3, 11:14 am, Shantanu <shaan.gu...@gmail.com> wrote:

Hi,

I have a netlist in which i have find out which nets are tied to VCC
or GND.
The list should contain hierarchial path of the net and status whether
tied to VCC or GND?

Please let me know how can i do that whether it requires any tool or
script.

Cheers!
Shaan

I'm not certain but you may want to investigate the Verilog Perl
module http://search.cpan.org/dist/Verilog-Perl. It might be able to
help you with finding this information. Otherwise, a commercial linter
should work as well.

 

[Muzaffer Kal]

On Mon, 3 Aug 2009 08:14:12 -0700 (PDT), Shantanu
<shaan.gupta@gmail.com> wrote:

Hi,

I have a netlist in which i have find out which nets are tied to VCC
or GND.
The list should contain hierarchial path of the net and status whether
tied to VCC or GND?

Please let me know how can i do that whether it requires any tool or
script.

If the reason you have to do this is for ERC purposes (ie your flow
has a rule which disallows gate inputs to be directly connected to
VCC/GND so they should be connected to some special cell outputs
instead) then you can probably enforce this rule within your back-end
toolset. Most back-ends support this feature directly by allowing you
to run a command to replace all such direct connections with correctly
inserted HI/LO cell outputs.
If your need is otherwise you can use the commonly available parsers
to write some scripts to get what you want.
-
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com