how to generate sdf file in cadence buildgates?

[Carson]

Hi,

I am a newbie in ASIC design. Right now, I am using Cadence Buildgates
to syntehsize my RTL verilog code. I can now generate timing and area
report, but I don't know how to generate the sdf file. (I am using
pks_shell). Any help will be highly appreciated.

 

[m]

On Sat, 14 May 2005 03:37:48 GMT, "Carson" <carson@ieee.org> wrote:

Hi,

I am a newbie in ASIC design. Right now, I am using Cadence Buildgates
to syntehsize my RTL verilog code. I can now generate timing and area
report, but I don't know how to generate the sdf file. (I am using
pks_shell). Any help will be highly appreciated.

Try "write_sdf". You can look at similar command with "help sdf"

 

[ka]

On Wed, 28 Jul 2004 09:23:44 -0700, "Carson" <carson@ieee.org> wrote:

Hi,

I am a newbie in ASIC design. Right now, I am using Cadence Buildgates
to syntehsize my RTL verilog code. I can now generate timing and area
report, but I don't know how to generate the sdf file. (I am using
pks_shell). Any help will be highly appreciated.


try "write_sdf" command.