Guest
i am having simple code in VHDL,
i am runing this in active hd 6.1,
the how to generate block diagram automatically for the given code
sir.
i.e this code is cascade of 3 flip-flops, so software to genetate
this
entity rsynch is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
d : in STD_LOGIC;
q : buffer STD_LOGIC
);
end rsynch;
--}} End of automatically maintained section
architecture arch_rsynch of rsynch is
signal temp1 : std_logic;
signal temp2 : std_logic;
begin
p1: process ( reset,clk)
begin
if reset = '1' then
q <= '0';
elsif (clk'event and clk ='1' ) then
temp1 <= d;
temp2 <= temp1;
q <=temp2;
end if ;
end process p1;
end arch_rsynch;
i am runing this in active hd 6.1,
the how to generate block diagram automatically for the given code
sir.
i.e this code is cascade of 3 flip-flops, so software to genetate
this
entity rsynch is
port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
d : in STD_LOGIC;
q : buffer STD_LOGIC
);
end rsynch;
--}} End of automatically maintained section
architecture arch_rsynch of rsynch is
signal temp1 : std_logic;
signal temp2 : std_logic;
begin
p1: process ( reset,clk)
begin
if reset = '1' then
q <= '0';
elsif (clk'event and clk ='1' ) then
temp1 <= d;
temp2 <= temp1;
q <=temp2;
end if ;
end process p1;
end arch_rsynch;
