How to generate blif files from Synopsys

Hi,

I need to generate a .blif file for my design. My design has both
combinational and sequential logic.
the write command in dc_shell generates the following file formats

1. .db (default) Synopsys internal format
2. .edif
3. equation
4. lsi (LSI corp. netlist format)
5. pla (Berkeley Espresso PLA format)
6. st (State transition)
7. td (Tegas Design Language)
8. Verilog
9. VHDL

The equation and pla formats need the design to be combinational only,
so I cannot generate those formats.

Does anyone know how to generate .blif output formats?