How to generate bits info for a record structure?

[Weng Tianxiang]

Hi,

I have a data record designed as follows:

type DATA_RECORD_t record
I1: unsigned(7 downto 0);
I2: unsigned(15 downto 0);
end record;

I want to get its bit number and don't want to manually calculate the bit number.

How can I do it?

Thank you.

Weng

 

[KJ]

It is not clear what you really want to do but if you assign the bits in the record appropriately you can access bits and ranges using attributes of the record such as I1'high, I1'low, I2'range. For example,

type DATA_RECORD_t record 
  I1: unsigned(7 downto 0); 
  I2: unsigned(23 downto 8); 
end record;

Kevin Jennings

 

[Weng Tianxiang]

On Thursday, February 13, 2020 at 4:53:45 PM UTC-8, KJ wrote:

It is not clear what you really want to do but if you assign the bits in the record appropriately you can access bits and ranges using attributes of the record such as I1'high, I1'low, I2'range. For example,

type DATA_RECORD_t record 
  I1: unsigned(7 downto 0); 
  I2: unsigned(23 downto 8); 
end record;

Kevin Jennings

Hi KJ,
Thank you for your answer.

I have a FIFO. Its data-in and data-out are data record. But a general FIFO definition has data-in and data-out specified as follows:

D_I : in unsigned(DATA_BITS-1 downto 0); -- data input

So I hope to have a general method that does not need to calculate record's bits.

Your suggested method may work, but has no big difference from manually bit counting.

Weng

 

[Rick C]

On Thursday, February 13, 2020 at 10:14:38 PM UTC-5, Weng Tianxiang wrote:

On Thursday, February 13, 2020 at 4:53:45 PM UTC-8, KJ wrote:
It is not clear what you really want to do but if you assign the bits in the record appropriately you can access bits and ranges using attributes of the record such as I1'high, I1'low, I2'range. For example,

type DATA_RECORD_t record 
  I1: unsigned(7 downto 0); 
  I2: unsigned(23 downto 8); 
end record;

Kevin Jennings

Hi KJ,
Thank you for your answer.

I have a FIFO. Its data-in and data-out are data record. But a general FIFO definition has data-in and data-out specified as follows:

D_I : in unsigned(DATA_BITS-1 downto 0); -- data input

So I hope to have a general method that does not need to calculate record's bits.

Your suggested method may work, but has no big difference from manually bit counting.

Weng

You need to set up an alias to equate type DATA_RECORD_t to the type for your unsigned. I don't use this often, so I don't recall the details at all. It may not even be an alias, but something else that lets you assign one to the other without a type mismatch.

This will not solve the problem you are looking for however. I don't think you can do what you are asking for. The only way to do that is to set the number of bits in DATA_RECORD_t from a constant and then use that constant where you need the number of bits such as in your FIFO.

If I understand what you are trying to do, this is the best way to do that as far as I am aware.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

[KJ]

On Thursday, February 13, 2020 at 10:14:38 PM UTC-5, Weng Tianxiang wrote:

I have a FIFO. Its data-in and data-out are data record. But a general FIFO definition has data-in and data-out specified as follows:

D_I : in unsigned(DATA_BITS-1 downto 0); -- data input

So I hope to have a general method that does not need to calculate record's bits.

Your suggested method may work, but has no big difference from manually bit counting.

Then what you will be needing at some point is a way to convert between your record and an unsigned. To do that, what I posted will be needed. You will also need to/from unsigned conversion functions. If you search this forum and comp.lang.vhdl for converting from records to/from std_logic_vector you will find several times where I've posted my solution to that part of the problem. That solution becomes part of the package where the record is defined.

If you're just trying to see how many bits will be needed in that unsigned, then you just need I1'length+I2'length. Again, a function can be written that returns the length by simply encapsulating that into a function. That function should be put into the same package as the record definition and the to/from unsigned functions. Then you would declare the FIFO in/out signals as:

signal FifoInputMyRecord, FifoOutputMyRecord: DATA_RECORD_t;
signal FifoInput, FifoOutput: unsigned(Length(FifoInputMyRecord)-1 downto 0);
FifoInput <= ToUnsigned(FifoInputMyRecord);
FifoOutputMyRecord <= FromUnsigned(FifoOutput);

This method works and requires zero changes if you change the number of bits in I1 or I2. If you add an element such as I3 to the record then those to/from/length functions will need to change to add in the contributions of the new I3 element.

There is no way to 'iterate' through the elements of a record if that's what you mean by 'manually bit counting'.

Kevin Jennings

 

[Rick C]

On Friday, February 14, 2020 at 7:26:56 AM UTC-5, KJ wrote:

There is no way to 'iterate' through the elements of a record if that's what you mean by 'manually bit counting'.

I think he is expecting some way for the tools to do the counting for him and not have to write the code that provides that info as you suggest.

Please remember that Weng is not very experienced in VHDL in the same way the rest of us are. He doesn't seem to actually get his hands dirty building systems, rather he approaches it from an academic perspective. This is the guy who got a patent for "inventing" that for tools to support wave pipelining that there would need to be commands added to the HDL and a module in the tools to handle this.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

 

[Weng Tianxiang]

Please remember that Weng is not very experienced in VHDL in the same way the rest of us are. He doesn't seem to actually get his hands dirty building systems, rather he approaches it from an academic perspective. This is the guy who got a patent for "inventing" that for tools to support wave pipelining that there would need to be commands added to the HDL and a module in the tools to handle this.

--

Rick C.

Rick,
I am laughing when you said about my experiences in HDL.

I, one person, designed:
1. the logic of a FPGA chip in a DMA board that was used for all solid state systems manufactured by EMC with the world highest data transmission rate 480Mb/s for a maximum 528Mb/s PCI bus;

2. The logic of dual FPGA chips for a communication control board for the Lincoln Laboratory of MIT that has 5 different types of buses in military standard;

3. The logic of dual FPGA chips for a communication control board for a side scanning radar of Lockheed-Martin that has 1,024 interrupt sources in military standard.

Based on my information from my employer, IBM and HP came to negotiate
to produce the DMA board, and finally EMC got the deal.

My HDL designs always use a very limited subset of VHDL and most of VHDL features is never used, the reason is the limited subset of VHDL meets all my usage requirements.

Now I am busy doing a large invention project which may include more than 50 patents, and the technology and HARDWARE ALGORITHMS developed will be used in all CPUs and FPGA, and by every electronic engineer in the world.

Rick,
I think you never hear the word "HARDWARE ALGORITHMS". Yes, that is what I am doing!

Here is my original VHDL source code for help:

type FIFO_DATA_t record
FIFO_p0 : FIFO_ID_t;
FIFO_p1 : FIFO_ID_t;
end record;

FIFO_ID_t is another defined record.

If a new attribute "size" is introduced, the problem would be very simply resolved:

constant FIFO_SIZE : integer := FIFO_DATA_t'size;

Thank you.

Weng

 

[Rick C]

On Friday, February 14, 2020 at 5:26:38 PM UTC-5, Weng Tianxiang wrote:

Now I am busy doing a large invention project which may include more than 50 patents, and the technology and HARDWARE ALGORITHMS developed will be used in all CPUs and FPGA, and by every electronic engineer in the world.

This is the sort of grandiose claims we are used to from Weng. Maybe I was wrong about his experience in real hardware, but it is understandable from the questions he comes here to ask.

Rick,
I think you never hear the word "HARDWARE ALGORITHMS". Yes, that is what I am doing!

Yes, that is what we all do! Welcome to the club.

Here is my original VHDL source code for help:

type FIFO_DATA_t record
FIFO_p0 : FIFO_ID_t;
FIFO_p1 : FIFO_ID_t;
end record;

FIFO_ID_t is another defined record.

If a new attribute "size" is introduced, the problem would be very simply resolved:

constant FIFO_SIZE : integer := FIFO_DATA_t'size;

Uh, you mean you want to change the name of the length attribute to size???

But that won't work on a record. Why don't you contact the VHDL committee and suggest it?

Unfortunately the use of such an attribute is very limited. Knowing the size in bits of a record still won't let you assign the record to an unsigned vector even if the length matches. You will need to create a procedure to do the conversion for you or you will need to write that code in your FIFO routine so it has a record input and an unsigned output or whatever you are trying to do.

This is not an issue of learning less common features of VHDL. This is a matter of not understanding how VHDL works at a basic level. That is why I mistakenly assumed you were a novice at actually using VHDL in real world designs. My mistake.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

 

[KJ]

Weng

type FIFO_DATA_t record 

  FIFO_p0 : FIFO_ID_t; 
  FIFO_p1 : FIFO_ID_t; 
end record; 

> FIFO_ID_t is another defined record. 

KJ: Very easy. All you need is to create a 'length' function for each new record type that you define. Then, instead of defining a new 'size' attribute and writing this...

constant FIFO_SIZE : integer := FIFO_DATA_t'size; 

You would write this instead...
constant FIFO_SIZE : integer := length(FIFO_DATA_t);

I already showed how to write the length function given your original record type with record elements of unsigned. The only thing different here is that your record elements are themselves custom record types. In this case you would write the length function for type FIFO_DATA_t to be length(FIFO_p0) + length(FIFO_p1).

You *might* be able to override the length attribute for your record types like you can override operators such as *, +, -, etc. but I have never actually tried that. Personally I like the look of calling a function rather than using an attribute. Either way is the nearly the same amount of typing, one extra keystroke for length() vs 'length.

Kevin Jennings

 

[Weng Tianxiang]

Unfortunately the use of such an attribute is very limited. Knowing the size in bits of a record still won't let you assign the record to an unsigned vector even if the length matches. You will need to create a procedure to do the conversion for you or you will need to write that code in your FIFO routine so it has a record input and an unsigned output or whatever you are trying to do.


--

Rick C.

Rick,

I know that you are an experienced VHDL designer that can be reflected from your above raised further problems if "size" attribute is introduced.

I really consider the problems you raised to design a special FIFO with record type data-in and data-out.

But I finally got the issue resolved by doing this way:


constant FIFO_SIZE : integer := FIFO_DATA_t'length;

signal FIFO_0 : FIFO_ID_t;
signal FIFO_1 : FIFO_ID_t;
signal FIFO_D_I : unsigned(FIFO_SIZE-1 downto 0);
signal FIFO_D_O : unsigned(FIFO_SIZE-1 downto 0);

FIFO_D_I <= FIFO_0 & FIFO_1; <-- OK? both sides have same width!

KJ,
> if you're just trying to see how many bits will be needed in that unsigned, then you just need I1'length+I2'length

I will use your suggested method: using LENGTH for an unsigned signal!

It would be better if attribute LENGTH can be extended to a record type which has only bit string literals.

Thank you.

Weng