how to generate a random time sequency clock signal?

[Paul]

Hi, greetings,

I am wondering how to generate a random time sequenty clock signal in
verilog, like 0100100010100101.

thanks.

 

[Mike Treseler]

Paul wrote:

I am wondering how to generate a random time sequenty clock signal in
verilog, like 0100100010100101.

Rotate it, but use it as a clock enable, not a clock.

-- Mike Treseler

 

[Mahurshi Akilla]

Mike Treseler wrote:

Paul wrote:

I am wondering how to generate a random time sequenty clock signal in
verilog, like 0100100010100101.

Rotate it, but use it as a clock enable, not a clock.

-- Mike Treseler

Hmm... maybe I am not seeing this right, but wouldn't that
provide the same thing for clock enable anyway? how would
that be random?

Mahurshi Akilla

 

[Mahurshi Akilla]

Mike Treseler wrote:

how would
that be random?

It wouldn't. I assumed the OP wanted to use
a fixed sequence. Some XOR feedback would
make it more random looking, but even that
will repeat at some point.

-- Mike Treseler

By XOR feedback, do you mean LFSRs ? I learned
in a class that they could be used to generate
pseudo random sequences (which are used to
test circuits)

Mahurshi Akilla

 

[Mike Treseler]

Mahurshi Akilla wrote:

Hmm... maybe I am not seeing this right, but wouldn't that
provide the same thing for clock enable anyway?

I expect that the OP would be better off
by *not* distributing a gapped clock.

how would
that be random?

It wouldn't. I assumed the OP wanted to use
a fixed sequence. Some XOR feedback would
make it more random looking, but even that
will repeat at some point.

-- Mike Treseler