How to generate a CSA tree?

[Sleep Mode]

Hi all,

I am trying to design a 16-bit integer multiplier in VHDL and I want to use
a Carry-Save-Adder (CSA) tree for generating the interim subproducts
and -then- with an additional CPA (or other) adder to add them to the final
32-bit product; i.e. I want to build a full-tree multiplier.

My question is whether there is some automatic (core) generator for the
CSA-tree interconnections since it is rather complicated to do it by hand...
If not, is there any fast method of drawing it manually (pen-and-paper) so
that I can translate it to VHDL later on?


Thanks in advance guys,
Chris

 

[fe]

My question is whether there is some automatic (core) generator for the
CSA-tree interconnections since it is rather complicated to do it by
hand...

It's very easy to implement but if you want a core generator you can use:

http://www.fysel.ntnu.no/modgen/

If not, is there any fast method of drawing it manually (pen-and-paper) so
that I can translate it to VHDL later on?

You can check on Ray Andraka's web site

http://www.andraka.com/multipli.htm

cheers
Pat

Thanks in advance guys,
Chris