how to force DC to use a specific cell ?

[whizkid]

hi all,
how to force DC to use a specific cell for specific part of the code
in verilog module. Power compiler is implementing my logic with XL
gate (low power, high delay) from TSMC library. I want to use X2 or X4
flop for only that part of the code in the total verilog module. How
can I do that??

By the way I cant instantiate the gate from cell library since the
clock is gated.
(becoz I want power compiler to insert clockgate circuitry in the
clock pin of the flop.)
Regards
whizkid

 

[m]

On 6 Nov 2004 06:42:00 -0800, whizkid@gamebox.net (whizkid) wrote:

hi all,
how to force DC to use a specific cell for specific part of the code
in verilog module. Power compiler is implementing my logic with XL
gate (low power, high delay) from TSMC library. I want to use X2 or X4
flop for only that part of the code in the total verilog module. How
can I do that??

By the way I cant instantiate the gate from cell library since the
clock is gated.
(becoz I want power compiler to insert clockgate circuitry in the
clock pin of the flop.)
Regards
whizkid

I am not sure why you think instantiating the flop will prevent the
PC to do clock-gating. But if that's really the case, you can always
upsize the flop after the PC is done before you start the CTS. Write
out the verilog, change the flop and continue with the rest of the
flow. I still think you should be able to instantiate the flop only
(the same type as the PC generates but with a higher drive) and let PC
handle the rest.

 

[Alexander Gnusin]

I am not sure why you think instantiating the flop will prevent the
PC to do clock-gating. But if that's really the case, you can always
upsize the flop after the PC is done before you start the CTS. Write
out the verilog, change the flop and continue with the rest of the
flow. I still think you should be able to instantiate the flop only
(the same type as the PC generates but with a higher drive) and let PC
handle the rest.

I believe, eventually you are going to do scan insertion. During scan
insertion, you may use the folowing command:

set_scan_register_type -exact -type <scanFF_cell_name> <chosen regs>
(see man page on this command)

I also don't think that it is a good idea to edit synthesised
gate-level verilog. It is error-prone and hard to repeat each time you
do re-synthesis. If you have to to modifications after synthesis - you
can do it with dc (or pc) - tcl and then add your modifications to the
synthesis script.
You can see an example of dc-tcl code on my site:
www.adeptix.com/tclforeda -> DC enhancements -> rebind_cell


Regards,
Alexander Gnusin

 

[newman]

whizkid@gamebox.net (whizkid) wrote in message news:<edfc084c.0411060642.1f87efc7@posting.google.com>...

hi all,
how to force DC to use a specific cell for specific part of the code
in verilog module. Power compiler is implementing my logic with XL
gate (low power, high delay) from TSMC library. I want to use X2 or X4
flop for only that part of the code in the total verilog module. How
can I do that??

By the way I cant instantiate the gate from cell library since the
clock is gated.
(becoz I want power compiler to insert clockgate circuitry in the
clock pin of the flop.)
Regards
whizkid

Whizkid,
Why are posting "ASIC" stuff to the "FPGA" newsgroup? Are you
porting a "FPGA" design to an "ASIC"?, or more likely using an FPGA to
sanity check an ASIC design. I suppose a small percentage of the group
has done both ASICs and FPGAs, I know I did in a prior lifetime, but
based on the number of FPGA seats people are suggesting, I suspect
that the percentage that do both is relatively small.

- regards
Newman

 

[Thomas Stanka]

whizkid@gamebox.net (whizkid) wrote:

how to force DC to use a specific cell for specific part of the code
in verilog module. Power compiler is implementing my logic with XL
gate (low power, high delay) from TSMC library. I want to use X2 or X4
flop for only that part of the code in the total verilog module. How
can I do that??

Why not instanciating the gate in rtl code and use a
synopsys_translate_off pragma? This task is very easy in VHDL. I'm not
familiar enough with Verilog to tell you the exact code, but expect,
that this task is (almost) as easy as in VHDL.

bye Thomas

 

[whizkid]

always@(posedge CLK or negedge RST) begin
if(!RST) begin
EN132 <= 1`b0;
end
else if(ENB) begin
EN132 <= n_EN132;
end
end

say in this is the piece of code...
If I instantiate a DFF from library what will I connect to the CLK pin
of the flop(coz I want to gate the clock).. well its possible to
instantiate the both the flop and the integrated clock gate cell from
the library.. Is that what u meant to say??


thanks
whizkid







mk<kal@delete.dspia.com> wrote in message news:<91tpo09fhc5n5bapiccnbk3ce9c4bpg44v@4ax.com>...

On 6 Nov 2004 06:42:00 -0800, whizkid@gamebox.net (whizkid) wrote:

hi all,
how to force DC to use a specific cell for specific part of the code
in verilog module. Power compiler is implementing my logic with XL
gate (low power, high delay) from TSMC library. I want to use X2 or X4
flop for only that part of the code in the total verilog module. How
can I do that??

By the way I cant instantiate the gate from cell library since the
clock is gated.
(becoz I want power compiler to insert clockgate circuitry in the
clock pin of the flop.)
Regards
whizkid

I am not sure why you think instantiating the flop will prevent the
PC to do clock-gating. But if that's really the case, you can always
upsize the flop after the PC is done before you start the CTS. Write
out the verilog, change the flop and continue with the rest of the
flow. I still think you should be able to instantiate the flop only
(the same type as the PC generates but with a higher drive) and let PC
handle the rest.