How to force an internal wire which is deep inside DUT hiera

O

One Cent

Guest
Hi,
I am interested to know how can i force an internal wire which is deep
inside DUT hierachy at top level testbench using VHDL design?
In verilog, i can write in this way at top level testbench as below:

initial
begin
force tb.design.memory.rx_buffer.enable_model = 1'b0;
#100;
force tb.design.memory.rx_buffer.enable_model = 1'b1;
end

But how can I do this in a VHDL testbench?

Thanks.
 
On 2 Jul., 03:58, One Cent <princess_ch...@hotmail.com> wrote:
Hi,
I am interested to know how can i force an internal wire which is deep
inside DUT hierachy at top level testbench using VHDL design?
In verilog, i can write in this way at top level testbench as below:

initial
begin
 force tb.design.memory.rx_buffer.enable_model = 1'b0;
 #100;
  force tb.design.memory.rx_buffer.enable_model = 1'b1;
end

But how can I do this in a VHDL testbench?

Thanks.
Click to expand...
Hi,
if you are using Modelsim you can use the SignalSpy functions.
There you can access signals(wires/regs) by providing their
hierarchical path in the system.
Do a search for it in the documentation. It's all well explained.

Have a nice simulation
Eilert
 
On Jul 2, 2:50 pm, backhus <goo...@twinmail.de> wrote:
On 2 Jul., 03:58, One Cent <princess_ch...@hotmail.com> wrote:

Hi,
I am interested to know how can i force an internal wire which is deep
inside DUT hierachy at top level testbench using VHDL design?
In verilog, i can write in this way at top level testbench as below:

initial
begin
 force tb.design.memory.rx_buffer.enable_model = 1'b0;
 #100;
  force tb.design.memory.rx_buffer.enable_model = 1'b1;
end

But how can I do this in a VHDL testbench?

Thanks.

Hi,
if you are using Modelsim you can use the SignalSpy functions.
There you can access signals(wires/regs) by providing their
hierarchical path in the system.
Do a search for it in the documentation. It's all well explained.

Have a nice simulation
  Eilert
Click to expand...
Thanks Eilert!
This reminds me the use of init_signal_spy function in Modelsim!!
Thanks again =)
 
"One Cent" <princess_chris@hotmail.com> wrote in message
news:9ddc6ae0-0082-4074-be7b-bd20a56801ca@g7g2000prg.googlegroups.com...
On Jul 2, 2:50 pm, backhus <goo...@twinmail.de> wrote:
On 2 Jul., 03:58, One Cent <princess_ch...@hotmail.com> wrote:

Hi,
I am interested to know how can i force an internal wire which is deep
inside DUT hierachy at top level testbench using VHDL design?
In verilog, i can write in this way at top level testbench as below:

initial
begin
force tb.design.memory.rx_buffer.enable_model = 1'b0;
#100;
force tb.design.memory.rx_buffer.enable_model = 1'b1;
end

But how can I do this in a VHDL testbench?

Thanks.

Hi,
if you are using Modelsim you can use the SignalSpy functions.
There you can access signals(wires/regs) by providing their
hierarchical path in the system.
Do a search for it in the documentation. It's all well explained.

Have a nice simulation
Eilert

Thanks Eilert!
This reminds me the use of init_signal_spy function in Modelsim!!
Click to expand...
And at the same time you might want to email your favourite Mentor support
engineer and ask him/her to raise an ER to get VHDL2008 hierarchical references
implemented ;-)

Hans
www.ht-lab.com
 
"NigelE" <nigel_elliot@mentor.com> wrote in message
news:6ee02237-3e7e-4e16-8b27-ec4e9191669b@q11g2000yqi.googlegroups.com...
On Jul 3, 8:47 am, "HT-Lab" <han...@ht-lab.com> wrote:
"One Cent" <princess_ch...@hotmail.com> wrote in message

news:9ddc6ae0-0082-4074-be7b-bd20a56801ca@g7g2000prg.googlegroups.com...
On Jul 2, 2:50 pm, backhus <goo...@twinmail.de> wrote:

...

And at the same time you might want to email your favourite Mentor support
engineer and ask him/her to raise an ER to get VHDL2008 hierarchical
references
implemented ;-)

Hanswww.ht-lab.com- Hide quoted text -

- Show quoted text -

It is already !

VHDL-2008 external names was implemented in 6.5
It works across mixed languages provided both ends are VHDL

- Nigel
Click to expand...
Hi Nigel,

You are right, I totally missed that one when I read the vhdl2008 technote. I
tried it out and it works great.

local_enable <= <<signal .u1.u2.enable_s : std_logic >>;

Thanks,
Hans
www.ht-lab.com
 
On Jul 3, 8:47 am, "HT-Lab" <han...@ht-lab.com> wrote:
"One Cent" <princess_ch...@hotmail.com> wrote in message

news:9ddc6ae0-0082-4074-be7b-bd20a56801ca@g7g2000prg.googlegroups.com...
On Jul 2, 2:50 pm, backhus <goo...@twinmail.de> wrote:





On 2 Jul., 03:58, One Cent <princess_ch...@hotmail.com> wrote:

Hi,
I am interested to know how can i force an internal wire which is deep
inside DUT hierachy at top level testbench using VHDL design?
In verilog, i can write in this way at top level testbench as below:

initial
begin
force tb.design.memory.rx_buffer.enable_model = 1'b0;
#100;
force tb.design.memory.rx_buffer.enable_model = 1'b1;
end

But how can I do this in a VHDL testbench?

Thanks.

Hi,
if you are using Modelsim you can use the SignalSpy functions.
There you can access signals(wires/regs) by providing their
hierarchical path in the system.
Do a search for it in the documentation. It's all well explained.

Have a nice simulation
Eilert

Thanks Eilert!
This reminds me the use of init_signal_spy function in Modelsim!!

And at the same time you might want to email your favourite Mentor support
engineer and ask him/her to raise an ER to get VHDL2008 hierarchical references
implemented ;-)

Hanswww.ht-lab.com- Hide quoted text -

- Show quoted text -
Click to expand...
It is already !

VHDL-2008 external names was implemented in 6.5
It works across mixed languages provided both ends are VHDL

- Nigel
 
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