How to find latches in Xilinx ISE 10.1

[RCIngham]

Greetings,

The synthesis report on my design tells me that I have caused 3 latches t
be created: 1 LDC and 2 LDP. I didn't intend to create any...

Rather frustratingly, the reports aren't telling me which signals ar
associated with these latches, so that I can fix my code! My colleague
can't remember what the trick is. Please can someone enlighten me?

Thanks in advance,
R.


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[Symon]

On 4/12/2010 5:14 PM, RCIngham wrote:

Greetings,

The synthesis report on my design tells me that I have caused 3 latches to
be created: 1 LDC and 2 LDP. I didn't intend to create any...

Rather frustratingly, the reports aren't telling me which signals are
associated with these latches, so that I can fix my code! My colleagues
can't remember what the trick is. Please can someone enlighten me?

Thanks in advance,
R.

Search through the EDIF file?

HTH, Syms.

 

[RCIngham]

On 4/12/2010 5:14 PM, RCIngham wrote:
Greetings,

The synthesis report on my design tells me that I have caused 3 latche
to
be created: 1 LDC and 2 LDP. I didn't intend to create any...

Rather frustratingly, the reports aren't telling me which signals are
associated with these latches, so that I can fix my code! My colleagues
can't remember what the trick is. Please can someone enlighten me?

Thanks in advance,
R.


Search through the EDIF file?

HTH, Syms.

What EDIF file? Or perhaps, which EDIF file?
And don't suggest the post-Synthesis gate-level netlist, either. Bee
through that and failed to find and LD* components...


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[HT-Lab]

If your design is not to vendor specific you can try QNS to see what it comes
back with,

Hans
www.ht-lab.com



"RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote in message
news:rv-dnR4A5Kl5217WnZ2dnUVZ_qednZ2d@giganews.com...

Greetings,

The synthesis report on my design tells me that I have caused 3 latches to
be created: 1 LDC and 2 LDP. I didn't intend to create any...

Rather frustratingly, the reports aren't telling me which signals are
associated with these latches, so that I can fix my code! My colleagues
can't remember what the trick is. Please can someone enlighten me?

Thanks in advance,
R.


---------------------------------------
Posted through http://www.FPGARelated.com

 

[backhus]

On 12 Apr., 18:59, "RCIngham"
<robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:

On 4/12/2010 5:14 PM, RCIngham wrote:
Greetings,

The synthesis report on my design tells me that I have caused 3 latches
to
be created: 1 LDC and 2 LDP. I didn't intend to create any...

Rather frustratingly, the reports aren't telling me which signals are
associated with these latches, so that I can fix my code! My colleagues
can't remember what the trick is. Please can someone enlighten me?

Thanks in advance,
R.

Search through the EDIF file?

HTH, Syms.

What EDIF file? Or perhaps, which EDIF file?
And don't suggest the post-Synthesis gate-level netlist, either. Been
through that and failed to find and LD* components...

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

Hi,
the synthesis report tells you at least in which module of your design
the latch is found.
The reasons are mostly cases without when others and ifs withut else
in combinatorical processes.
(or conditional assignments outside of processes)

These should be easy to identify.
You shouldn't have too many combinatorical processes anyway.

Have a nice synthesis
Eilert

 

[RCIngham]

On 12 Apr., 18:59, "RCIngham"
robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
On 4/12/2010 5:14 PM, RCIngham wrote:
Greetings,

The synthesis report on my design tells me that I have caused
latche=
s
to
be created: 1 LDC and 2 LDP. I didn't intend to create any...

Rather frustratingly, the reports aren't telling me which signal
are
associated with these latches, so that I can fix my code! M
colleague=
s
can't remember what the trick is. Please can someone enlighten me?

Thanks in advance,
R.

Search through the EDIF file?

HTH, Syms.

What EDIF file? Or perhaps, which EDIF file?
And don't suggest the post-Synthesis gate-level netlist, either. Been
through that and failed to find and LD* components...

--------------------------------------- =A0 =A0 =A0 =A0
Posted throughhttp://www.FPGARelated.com

Hi,
the synthesis report tells you at least in which module of your design
the latch is found.
The reasons are mostly cases without when others and ifs withut else
in combinatorical processes.
(or conditional assignments outside of processes)

These should be easy to identify.
You shouldn't have too many combinatorical processes anyway.

Have a nice synthesis
Eilert

I've been through the .SYR file several times, and there is no such report
Is there a missing command switch in the script?

Perhaps they are in the .NGC file relating to the MicroBlaze processor. A
this is a reused item, why were they not spotted before? I'll try t
synthesize some of the blocks separately...

Grrrr!




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[whygee]

RCIngham wrote:

Perhaps they are in the .NGC file relating to the MicroBlaze processor. As
this is a reused item, why were they not spotted before? I'll try to
synthesize some of the blocks separately...

I think that I have read somewhere (where ? from another thread on
latch inference ?) that the Microblaze core uses a few latches.
So this could be a valid theory.

You could test it by replacing your MB core with a dumb one,
and see if the latches are still there.

Grrrr!
don't worry... it wouldn't change anything.

yg
--
http://ygdes.com / http://yasep.org

 

[RCIngham]

RCIngham wrote:
Perhaps they are in the .NGC file relating to the MicroBlaze processor
As
this is a reused item, why were they not spotted before? I'll try to
synthesize some of the blocks separately...

I think that I have read somewhere (where ? from another thread on
latch inference ?) that the Microblaze core uses a few latches.
So this could be a valid theory.

You could test it by replacing your MB core with a dumb one,
and see if the latches are still there.

A separate synthesis of the MB core yields the 3 latches, as does
synthesis of one of the other designs using the same MB.

Probably explains why no useful warnings in the Synthesis Report.

"Onward & Upward"


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[Martin Thompson]

"RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> writes:

Greetings,

The synthesis report on my design tells me that I have caused 3 latches to
be created: 1 LDC and 2 LDP. I didn't intend to create any...

Rather frustratingly, the reports aren't telling me which signals are
associated with these latches, so that I can fix my code! My colleagues
can't remember what the trick is. Please can someone enlighten me?

If you haven't found them yet (or for anyone later on finding this
thread), you could try our (free) tool which will narrow things down to
which module the latches are in.

http://www.conekt.net/fpgaoptim.html

It's how I first noticed that Microblaze has a few latches in it

Cheers,
Martin

--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

 

[whygee]

RCIngham wrote:

A separate synthesis of the MB core yields the 3 latches, as does a
synthesis of one of the other designs using the same MB.

Probably explains why no useful warnings in the Synthesis Report.

I'm happy that I have helped you !

yg
--
http://ygdes.com / http://yasep.org

 

[gcary]

I found this thread when searching for a way to find a latch in my design.
I discovered another very easy way to find latches in 10.1 of ISE.
placed and routed my design and then ran PlanAhead. Go to Edit -> Find
and choose "Instances". The criteria should be "Type" "is" "Latch". I
found the latch in the blink of an eye. Turned out to be a Chipscope IL
that had a latch in it.

Greg




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